Searched refs:ReplaceReg (Results 1 – 6 of 6) sorted by relevance
| /external/mesa3d/src/gallium/drivers/r300/compiler/ |
| D | radeon_compiler_util.c | 370 const struct rc_src_register * ReplaceReg; member
399 if (!d->ReplaceRemoved && src == d->ReplaceReg) { in can_use_presub_read_cb()
445 d.ReplaceReg = replace_reg; in rc_inst_can_use_presub()
|
| /external/llvm-project/llvm/lib/CodeGen/ |
| D | ModuloSchedule.cpp | 1167 unsigned ReplaceReg = 0; in rewriteScheduledInstr() local
1172 ReplaceReg = PrevReg; in rewriteScheduledInstr()
1175 ReplaceReg = PrevReg; in rewriteScheduledInstr()
1177 ReplaceReg = NewReg; in rewriteScheduledInstr()
1182 ReplaceReg = NewReg; in rewriteScheduledInstr()
1184 ReplaceReg = NewReg; in rewriteScheduledInstr()
1186 ReplaceReg = NewReg; in rewriteScheduledInstr()
1187 if (ReplaceReg) { in rewriteScheduledInstr()
1188 MRI.constrainRegClass(ReplaceReg, MRI.getRegClass(OldReg)); in rewriteScheduledInstr()
1189 UseOp.setReg(ReplaceReg); in rewriteScheduledInstr()
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/ |
| D | ModuloSchedule.cpp | 1163 unsigned ReplaceReg = 0; in rewriteScheduledInstr() local
1168 ReplaceReg = PrevReg; in rewriteScheduledInstr()
1171 ReplaceReg = PrevReg; in rewriteScheduledInstr()
1173 ReplaceReg = NewReg; in rewriteScheduledInstr()
1178 ReplaceReg = NewReg; in rewriteScheduledInstr()
1180 ReplaceReg = NewReg; in rewriteScheduledInstr()
1182 ReplaceReg = NewReg; in rewriteScheduledInstr()
1183 if (ReplaceReg) { in rewriteScheduledInstr()
1184 MRI.constrainRegClass(ReplaceReg, MRI.getRegClass(OldReg)); in rewriteScheduledInstr()
1185 UseOp.setReg(ReplaceReg); in rewriteScheduledInstr()
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
| D | AMDGPUMachineCFGStructurizer.cpp | 1116 unsigned *ReplaceReg);
1120 SmallVector<unsigned, 2> &PHIIndices, unsigned *ReplaceReg);
1449 unsigned *ReplaceReg) { in shrinkPHI() argument
1450 return shrinkPHI(PHI, 0, nullptr, PHIIndices, ReplaceReg); in shrinkPHI()
1457 unsigned *ReplaceReg) { in shrinkPHI() argument
1479 *ReplaceReg = getPHISourceReg(PHI, SingleExternalEntryIndex); in shrinkPHI()
2445 unsigned ReplaceReg; in splitLoopPHI() local
2447 if (shrinkPHI(PHI, PHIRegionIndices, &ReplaceReg)) { in splitLoopPHI()
2448 PHISource = ReplaceReg; in splitLoopPHI()
|
| /external/llvm-project/llvm/lib/Target/AMDGPU/ |
| D | AMDGPUMachineCFGStructurizer.cpp | 1117 unsigned *ReplaceReg);
1121 SmallVector<unsigned, 2> &PHIIndices, unsigned *ReplaceReg);
1450 unsigned *ReplaceReg) { in shrinkPHI() argument
1451 return shrinkPHI(PHI, 0, nullptr, PHIIndices, ReplaceReg); in shrinkPHI()
1458 unsigned *ReplaceReg) { in shrinkPHI() argument
1480 *ReplaceReg = getPHISourceReg(PHI, SingleExternalEntryIndex); in shrinkPHI()
2446 unsigned ReplaceReg; in splitLoopPHI() local
2448 if (shrinkPHI(PHI, PHIRegionIndices, &ReplaceReg)) { in splitLoopPHI()
2449 PHISource = ReplaceReg; in splitLoopPHI()
|
| /external/llvm/lib/CodeGen/ |
| D | MachinePipeliner.cpp | 3273 unsigned ReplaceReg = 0; in rewriteScheduledInstr() local
3278 ReplaceReg = PrevReg; in rewriteScheduledInstr()
3281 ReplaceReg = PrevReg; in rewriteScheduledInstr()
3283 ReplaceReg = NewReg; in rewriteScheduledInstr()
3289 ReplaceReg = NewReg; in rewriteScheduledInstr()
3291 ReplaceReg = NewReg; in rewriteScheduledInstr()
3293 ReplaceReg = NewReg; in rewriteScheduledInstr()
3294 if (ReplaceReg) { in rewriteScheduledInstr()
3295 MRI.constrainRegClass(ReplaceReg, MRI.getRegClass(OldReg)); in rewriteScheduledInstr()
3296 UseOp.setReg(ReplaceReg); in rewriteScheduledInstr()
|