| /external/llvm-project/llvm/lib/Target/X86/ |
| D | X86SchedSkylakeClient.td | 97 let ResourceCycles = Res;
105 let ResourceCycles = !listconcat([1], Res);
417 let ResourceCycles = [2];
482 let ResourceCycles = [3];
487 let ResourceCycles = [3,1];
494 let ResourceCycles = [4,3,1,1];
499 let ResourceCycles = [4,3,1,1,1];
506 let ResourceCycles = [3];
511 let ResourceCycles = [3,1];
518 let ResourceCycles = [4,3,1];
[all …]
|
| D | X86SchedBroadwell.td | 98 let ResourceCycles = Res;
106 let ResourceCycles = !listconcat([1], Res);
427 let ResourceCycles = [2];
491 let ResourceCycles = [3];
496 let ResourceCycles = [3,1];
503 let ResourceCycles = [4,3,1,1];
508 let ResourceCycles = [4,3,1,1,1];
515 let ResourceCycles = [3];
520 let ResourceCycles = [3,1];
527 let ResourceCycles = [4,3,1];
[all …]
|
| D | X86SchedHaswell.td | 103 let ResourceCycles = Res;
111 let ResourceCycles = !listconcat([1], Res);
468 let ResourceCycles = [2];
491 let ResourceCycles = [3];
496 let ResourceCycles = [3,1];
503 let ResourceCycles = [4,3,1,1];
508 let ResourceCycles = [4,3,1,1,1];
515 let ResourceCycles = [3];
520 let ResourceCycles = [3,1];
527 let ResourceCycles = [4,3,1];
[all …]
|
| D | X86SchedSkylakeServer.td | 97 let ResourceCycles = Res;
105 let ResourceCycles = !listconcat([1], Res);
418 let ResourceCycles = [2];
483 let ResourceCycles = [3];
488 let ResourceCycles = [3,1];
495 let ResourceCycles = [4,3,1,1];
500 let ResourceCycles = [4,3,1,1,1];
507 let ResourceCycles = [3];
512 let ResourceCycles = [3,1];
519 let ResourceCycles = [4,3,1];
[all …]
|
| D | X86ScheduleAtom.td | 65 let ResourceCycles = RRRes;
72 let ResourceCycles = RMRes;
121 let ResourceCycles = [2];
125 let ResourceCycles = [2];
458 def : WriteRes<WriteFMOVMSK, [AtomPort0]> { let Latency = 3; let ResourceCycles = [3]; }
459 def : WriteRes<WriteVecMOVMSK, [AtomPort0]> { let Latency = 3; let ResourceCycles = [3]; }
461 def : WriteRes<WriteMMXMOVMSK, [AtomPort0]> { let Latency = 3; let ResourceCycles = [3]; }
491 def : WriteRes<WriteLDMXCSR, [AtomPort01]> { let Latency = 5; let ResourceCycles = [5]; }
492 def : WriteRes<WriteSTMXCSR, [AtomPort01]> { let Latency = 15; let ResourceCycles = [15]; }
501 let ResourceCycles = [1];
[all …]
|
| D | X86SchedSandyBridge.td | 93 let ResourceCycles = Res;
101 let ResourceCycles = !listconcat([1], Res);
473 let ResourceCycles = [3];
478 let ResourceCycles = [3,1];
484 let ResourceCycles = [8];
488 let ResourceCycles = [7, 1];
495 let ResourceCycles = [3];
500 let ResourceCycles = [3,1];
506 let ResourceCycles = [8];
510 let ResourceCycles = [7, 1];
[all …]
|
| D | X86ScheduleBdVer2.td | 195 let ResourceCycles = Res;
268 def : WriteRes<WriteLoad, [PdLoad]> { let Latency = 5; let ResourceCycles = [2]; }
271 def : WriteRes<WriteMove, [PdEX01]> { let ResourceCycles = [2]; }
276 def : WriteRes<WriteSTMXCSR, [PdStore]> { let NumMicroOps = 2; let ResourceCycles = [18]; }
310 let ResourceCycles = [375];
318 def : WriteRes<WriteNop, [PdEX01]> { let ResourceCycles = [2]; }
328 let ResourceCycles = [3, 2, 1];
335 let ResourceCycles = [88];
342 let ResourceCycles = [2];
354 let ResourceCycles = [3, 3];
[all …]
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/ |
| D | X86SchedSkylakeClient.td | 97 let ResourceCycles = Res;
105 let ResourceCycles = !listconcat([1], Res);
414 let ResourceCycles = [2];
479 let ResourceCycles = [3];
484 let ResourceCycles = [3,1];
491 let ResourceCycles = [4,3,1,1];
496 let ResourceCycles = [4,3,1,1,1];
503 let ResourceCycles = [3];
508 let ResourceCycles = [3,1];
515 let ResourceCycles = [4,3,1];
[all …]
|
| D | X86SchedBroadwell.td | 98 let ResourceCycles = Res;
106 let ResourceCycles = !listconcat([1], Res);
424 let ResourceCycles = [2];
488 let ResourceCycles = [3];
493 let ResourceCycles = [3,1];
500 let ResourceCycles = [4,3,1,1];
505 let ResourceCycles = [4,3,1,1,1];
512 let ResourceCycles = [3];
517 let ResourceCycles = [3,1];
524 let ResourceCycles = [4,3,1];
[all …]
|
| D | X86SchedHaswell.td | 103 let ResourceCycles = Res;
111 let ResourceCycles = !listconcat([1], Res);
465 let ResourceCycles = [2];
488 let ResourceCycles = [3];
493 let ResourceCycles = [3,1];
500 let ResourceCycles = [4,3,1,1];
505 let ResourceCycles = [4,3,1,1,1];
512 let ResourceCycles = [3];
517 let ResourceCycles = [3,1];
524 let ResourceCycles = [4,3,1];
[all …]
|
| D | X86SchedSkylakeServer.td | 97 let ResourceCycles = Res;
105 let ResourceCycles = !listconcat([1], Res);
415 let ResourceCycles = [2];
480 let ResourceCycles = [3];
485 let ResourceCycles = [3,1];
492 let ResourceCycles = [4,3,1,1];
497 let ResourceCycles = [4,3,1,1,1];
504 let ResourceCycles = [3];
509 let ResourceCycles = [3,1];
516 let ResourceCycles = [4,3,1];
[all …]
|
| D | X86ScheduleAtom.td | 65 let ResourceCycles = RRRes;
72 let ResourceCycles = RMRes;
121 let ResourceCycles = [2];
125 let ResourceCycles = [2];
455 def : WriteRes<WriteFMOVMSK, [AtomPort0]> { let Latency = 3; let ResourceCycles = [3]; }
456 def : WriteRes<WriteVecMOVMSK, [AtomPort0]> { let Latency = 3; let ResourceCycles = [3]; }
458 def : WriteRes<WriteMMXMOVMSK, [AtomPort0]> { let Latency = 3; let ResourceCycles = [3]; }
488 def : WriteRes<WriteLDMXCSR, [AtomPort01]> { let Latency = 5; let ResourceCycles = [5]; }
489 def : WriteRes<WriteSTMXCSR, [AtomPort01]> { let Latency = 15; let ResourceCycles = [15]; }
498 let ResourceCycles = [1];
[all …]
|
| D | X86SchedSandyBridge.td | 93 let ResourceCycles = Res;
101 let ResourceCycles = !listconcat([1], Res);
470 let ResourceCycles = [3];
475 let ResourceCycles = [3,1];
481 let ResourceCycles = [8];
485 let ResourceCycles = [7, 1];
492 let ResourceCycles = [3];
497 let ResourceCycles = [3,1];
503 let ResourceCycles = [8];
507 let ResourceCycles = [7, 1];
[all …]
|
| D | X86ScheduleBdVer2.td | 195 let ResourceCycles = Res;
268 def : WriteRes<WriteLoad, [PdLoad]> { let Latency = 5; let ResourceCycles = [2]; }
271 def : WriteRes<WriteMove, [PdEX01]> { let ResourceCycles = [2]; }
276 def : WriteRes<WriteSTMXCSR, [PdStore]> { let NumMicroOps = 2; let ResourceCycles = [18]; }
310 let ResourceCycles = [375];
318 def : WriteRes<WriteNop, [PdEX01]> { let ResourceCycles = [2]; }
328 let ResourceCycles = [3, 2, 1];
335 let ResourceCycles = [88];
342 let ResourceCycles = [2];
354 let ResourceCycles = [3, 3];
[all …]
|
| /external/llvm/lib/Target/X86/ |
| D | X86ScheduleBtVer2.td | 115 let ResourceCycles = [4];
121 let ResourceCycles = [1, 25];
125 let ResourceCycles = [1, 1, 25];
179 let ResourceCycles = [1, 1, 21];
183 let ResourceCycles = [1, 1, 21];
188 let ResourceCycles = [1, 1, 19];
192 let ResourceCycles = [1, 1, 19];
202 let ResourceCycles = [2];
206 let ResourceCycles = [1, 2];
220 let ResourceCycles = [2];
[all …]
|
| D | X86ScheduleSLM.td | 94 let ResourceCycles = [1, 25];
98 let ResourceCycles = [1, 1, 25];
115 let ResourceCycles = [1, 2];
119 let ResourceCycles = [1, 1, 2];
124 let ResourceCycles = [1, 34];
128 let ResourceCycles = [1, 1, 34];
144 let ResourceCycles = [13];
148 let ResourceCycles = [13, 1];
154 let ResourceCycles = [17];
158 let ResourceCycles = [17, 1];
[all …]
|
| D | X86SchedSandyBridge.td | 108 let ResourceCycles = [1, 10];
112 let ResourceCycles = [1, 1, 10];
129 let ResourceCycles = [1, 1];
133 let ResourceCycles = [1, 1, 1];
145 let ResourceCycles = [1, 1];
149 let ResourceCycles = [1, 1, 1];
153 let ResourceCycles = [1, 1, 1];
157 let ResourceCycles = [1, 1, 1, 1];
164 let ResourceCycles = [3];
168 let ResourceCycles = [3, 1];
[all …]
|
| D | X86SchedHaswell.td | 120 let ResourceCycles = [1, 10];
124 let ResourceCycles = [1, 1, 10];
143 let ResourceCycles = [2];
147 let ResourceCycles = [2, 1];
161 let ResourceCycles = [2];
165 let ResourceCycles = [2, 1];
170 let ResourceCycles = [2, 1];
174 let ResourceCycles = [2, 1, 1];
179 let ResourceCycles = [1, 2];
183 let ResourceCycles = [1, 1, 2];
[all …]
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/MCA/ |
| D | Support.cpp | 23 ResourceCycles &ResourceCycles::operator+=(const ResourceCycles &RHS) { in operator +=()
94 unsigned ResourceCycles = ProcResourceUsage[I]; in computeBlockRThroughput() local
95 if (!ResourceCycles) in computeBlockRThroughput()
99 double Throughput = static_cast<double>(ResourceCycles) / MCDesc.NumUnits; in computeBlockRThroughput()
|
| /external/llvm-project/llvm/lib/MCA/ |
| D | Support.cpp | 23 ResourceCycles &ResourceCycles::operator+=(const ResourceCycles &RHS) { in operator +=()
94 unsigned ResourceCycles = ProcResourceUsage[I]; in computeBlockRThroughput() local
95 if (!ResourceCycles) in computeBlockRThroughput()
99 double Throughput = static_cast<double>(ResourceCycles) / MCDesc.NumUnits; in computeBlockRThroughput()
|
| /external/llvm-project/llvm/include/llvm/MCA/ |
| D | Support.h | 50 class ResourceCycles {
54 ResourceCycles() : Numerator(0), Denominator(1) {} in ResourceCycles() function
55 ResourceCycles(unsigned Cycles, unsigned ResourceUnits = 1)
69 ResourceCycles &operator+=(const ResourceCycles &RHS);
|
| /external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/MCA/ |
| D | Support.h | 50 class ResourceCycles {
54 ResourceCycles() : Numerator(0), Denominator(1) {} in ResourceCycles() function
55 ResourceCycles(unsigned Cycles, unsigned ResourceUnits = 1)
69 ResourceCycles &operator+=(const ResourceCycles &RHS);
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/PowerPC/ |
| D | PPCScheduleP9.td | 230 let ResourceCycles = [8];
235 let ResourceCycles = [8];
240 let ResourceCycles = [8];
264 let ResourceCycles = [5];
269 let ResourceCycles = [8];
274 let ResourceCycles = [8];
279 let ResourceCycles = [5];
284 let ResourceCycles = [10];
289 let ResourceCycles = [10];
294 let ResourceCycles = [8];
[all …]
|
| /external/llvm-project/llvm/lib/Target/PowerPC/ |
| D | PPCScheduleP9.td | 231 let ResourceCycles = [8];
236 let ResourceCycles = [8];
241 let ResourceCycles = [8];
265 let ResourceCycles = [5];
270 let ResourceCycles = [8];
275 let ResourceCycles = [8];
280 let ResourceCycles = [5];
285 let ResourceCycles = [10];
290 let ResourceCycles = [10];
295 let ResourceCycles = [8];
[all …]
|
| /external/llvm-project/llvm/lib/Target/ARM/ |
| D | ARMScheduleA57WriteRes.td | 31 let ResourceCycles = [17]; }
33 let ResourceCycles = [18]; }
35 let ResourceCycles = [19]; }
37 let ResourceCycles = [20]; }
40 let ResourceCycles = [1]; }
42 let ResourceCycles = [1]; }
48 let ResourceCycles = [1]; }
50 let ResourceCycles = [32]; }
52 let ResourceCycles = [32]; }
54 let ResourceCycles = [35]; }
[all …]
|