| /external/capstone/arch/ARM/ |
| D | ARMAddressingModes.h | 341 int Rot; in getT2SOImmVal() local
348 Rot = getT2SOImmValRotateVal(Arg); in getT2SOImmVal()
349 if (Rot != -1) in getT2SOImmVal()
350 return Rot; in getT2SOImmVal()
|
| D | ARMInstPrinter.c | 2344 unsigned Rot = (MCOperand_getImm(Op) & 0xF00) >> 7; in printModImmOperand() local
2359 Rotated = rotr32(Bits, Rot); in printModImmOperand()
2384 SStream_concat(O, "#%u, #%u", Bits, Rot); in printModImmOperand()
2390 MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = Rot; in printModImmOperand()
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/MCTargetDesc/ |
| D | ARMAddressingModes.h | 313 int Rot = getT2SOImmValRotateVal(Arg); in getT2SOImmVal() local
314 if (Rot != -1) in getT2SOImmVal()
315 return Rot; in getT2SOImmVal()
|
| D | ARMInstPrinter.cpp | 1376 unsigned Rot = (Op.getImm() & 0xF00) >> 7; in printModImmOperand() local
1390 int32_t Rotated = ARM_AM::rotr32(Bits, Rot); in printModImmOperand()
1404 << Rot << markup(">"); in printModImmOperand()
|
| /external/llvm-project/llvm/lib/Target/ARM/MCTargetDesc/ |
| D | ARMAddressingModes.h | 327 int Rot = getT2SOImmValRotateVal(Arg); in getT2SOImmVal() local
328 if (Rot != -1) in getT2SOImmVal()
329 return Rot; in getT2SOImmVal()
|
| D | ARMInstPrinter.cpp | 1376 unsigned Rot = (Op.getImm() & 0xF00) >> 7; in printModImmOperand() local
1390 int32_t Rotated = ARM_AM::rotr32(Bits, Rot); in printModImmOperand()
1404 << Rot << markup(">"); in printModImmOperand()
|
| /external/llvm/lib/Target/ARM/MCTargetDesc/ |
| D | ARMAddressingModes.h | 321 int Rot = getT2SOImmValRotateVal(Arg); in getT2SOImmVal() local
322 if (Rot != -1) in getT2SOImmVal()
323 return Rot; in getT2SOImmVal()
|
| /external/llvm/lib/Target/ARM/InstPrinter/ |
| D | ARMInstPrinter.cpp | 1415 unsigned Rot = (Op.getImm() & 0xF00) >> 7; in printModImmOperand() local
1429 int32_t Rotated = ARM_AM::rotr32(Bits, Rot); in printModImmOperand()
1443 << Rot << markup(">"); in printModImmOperand()
|
| /external/swiftshader/third_party/subzero/src/ |
| D | IceInstARM32.cpp | 377 for (int Rot = 1; Rot < 16; Rot++) { in canHoldImm() local
378 uint32_t Imm8 = Utils::rotateLeft32(Immediate, 2 * Rot); in canHoldImm()
380 *RotateAmt = Rot; in canHoldImm()
|
| D | IceAssemblerARM32.cpp | 1193 IValueT Rot = encodeRotation(Rotation); in emitSignExtend() local
1194 if (!Utils::IsUint(2, Rot)) in emitSignExtend()
1199 (Rot << kRotationShift) | B6 | B5 | B4 | (Rm << kRmShift); in emitSignExtend()
|
| /external/llvm/unittests/ADT/ |
| D | APIntTest.cpp | 825 APInt Rot(256, "3fff80000000000000000000000000000000000040008000", 16); in TEST() local
826 EXPECT_EQ(Rot, Big.rotr(144)); in TEST()
|
| /external/llvm-project/llvm/lib/Target/Hexagon/ |
| D | HexagonISelLoweringHVX.cpp | 1198 SDValue Rot = getInstr(Hexagon::V6_valignbi, dl, ByteTy, in compressHvxPred() local
1200 SDValue Vor = DAG.getNode(ISD::OR, dl, ByteTy, {Vrmpy, Rot}); in compressHvxPred()
2222 SDValue Rot = DAG.getNode(ISD::ADD, dl, ty(Rot0), {Rot0, Rot1}); in PerformHvxDAGCombine() local
2223 return DAG.getNode(HexagonISD::VROR, dl, ty(Op), {Vec, Rot}); in PerformHvxDAGCombine()
|
| /external/icu/icu4c/source/data/zone/ |
| D | pcm.txt | 625 ec{"Rotẹ́ra"}
1773 ls{"Rotẹ́ra Taim"}
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Transforms/InstCombine/ |
| D | InstCombineSelect.cpp | 2791 if (Instruction *Rot = foldSelectRotate(SI)) in visitSelectInst() local
2792 return Rot; in visitSelectInst()
|
| /external/llvm-project/llvm/unittests/ADT/ |
| D | APIntTest.cpp | 1540 APInt Rot(256, "3fff80000000000000030000000000000000000040008000", 16); in TEST() local
1541 EXPECT_EQ(Rot, Big.rotr(144)); in TEST()
|
| /external/llvm/lib/Target/ARM/AsmParser/ |
| D | ARMAsmParser.cpp | 553 unsigned Rot; member
1857 Inst.addOperand(MCOperand::createImm(ModImm.Bits | (ModImm.Rot << 7))); in addModImmOperands()
2693 static std::unique_ptr<ARMOperand> CreateModImm(unsigned Bits, unsigned Rot, in CreateModImm() argument
2697 Op->ModImm.Rot = Rot; in CreateModImm()
2967 << ModImm.Rot << ")>"; in print()
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/AsmParser/ |
| D | ARMAsmParser.cpp | 824 unsigned Rot; member
2485 Inst.addOperand(MCOperand::createImm(ModImm.Bits | (ModImm.Rot << 7))); in addModImmOperands()
3504 static std::unique_ptr<ARMOperand> CreateModImm(unsigned Bits, unsigned Rot, in CreateModImm() argument
3508 Op->ModImm.Rot = Rot; in CreateModImm()
3823 << ModImm.Rot << ")>"; in print()
|
| /external/llvm-project/llvm/lib/Target/ARM/AsmParser/ |
| D | ARMAsmParser.cpp | 890 unsigned Rot; member
2551 Inst.addOperand(MCOperand::createImm(ModImm.Bits | (ModImm.Rot << 7))); in addModImmOperands()
3570 static std::unique_ptr<ARMOperand> CreateModImm(unsigned Bits, unsigned Rot, in CreateModImm() argument
3574 Op->ModImm.Rot = Rot; in CreateModImm()
3888 << ModImm.Rot << ")>"; in print()
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Transforms/Utils/ |
| D | SimplifyCFG.cpp | 5680 auto *Rot = Builder.CreateOr(LShr, Shl); in ReduceSwitchRange() local
5681 SI->replaceUsesOfWith(SI->getCondition(), Rot); in ReduceSwitchRange()
|
| /external/llvm-project/llvm/lib/Transforms/Utils/ |
| D | SimplifyCFG.cpp | 5834 auto *Rot = Builder.CreateOr(LShr, Shl); in ReduceSwitchRange() local
5835 SI->replaceUsesOfWith(SI->getCondition(), Rot); in ReduceSwitchRange()
|
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | DAGCombiner.cpp | 3857 if (SDNode *Rot = MatchRotate(N0, N1, SDLoc(N))) in visitOR() local
3858 return SDValue(Rot, 0); in visitOR()
4067 SDValue Rot = DAG.getNode(HasROTL ? ISD::ROTL : ISD::ROTR, DL, VT, in MatchRotate() local
4088 Rot = DAG.getNode(ISD::AND, DL, VT, Rot, Mask); in MatchRotate()
4091 return Rot.getNode(); in MatchRotate()
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/SelectionDAG/ |
| D | DAGCombiner.cpp | 5942 if (SDValue Rot = MatchRotate(N0, N1, SDLoc(N))) in visitOR() local
5943 return Rot; in visitOR()
6268 if (SDValue Rot = MatchRotate(LHS.getOperand(0), RHS.getOperand(0), DL)) { in MatchRotate() local
6269 return DAG.getNode(ISD::TRUNCATE, SDLoc(LHS), LHS.getValueType(), Rot); in MatchRotate()
6337 SDValue Rot = DAG.getNode(HasROTL ? ISD::ROTL : ISD::ROTR, DL, VT, in MatchRotate() local
6356 Rot = DAG.getNode(ISD::AND, DL, VT, Rot, Mask); in MatchRotate()
6359 return Rot; in MatchRotate()
|
| /external/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| D | DAGCombiner.cpp | 6355 if (SDValue Rot = MatchRotate(N0, N1, SDLoc(N))) in visitOR() local
6356 return Rot; in visitOR()
6758 if (SDValue Rot = MatchRotate(LHS.getOperand(0), RHS.getOperand(0), DL)) { in MatchRotate() local
6759 return DAG.getNode(ISD::TRUNCATE, SDLoc(LHS), LHS.getValueType(), Rot); in MatchRotate()
|
| /external/kotlinx.coroutines/benchmarks/src/jmh/resources/ |
| D | words.shakespeare.txt.gz | 1a
2A
3Aaron
4AARON
5abaissiez
6abandon
7abandoned
8abase
9Abase
10 ... |
| /external/llvm-project/llvm/lib/Target/X86/ |
| D | X86ISelLowering.cpp | 12360 SDValue Rot = DAG.getNode(ISD::OR, DL, RotateVT, SHL, SRL); in lowerShuffleAsBitRotate() local
12361 return DAG.getBitcast(VT, Rot); in lowerShuffleAsBitRotate()
12364 SDValue Rot = in lowerShuffleAsBitRotate() local
12367 return DAG.getBitcast(VT, Rot); in lowerShuffleAsBitRotate()
|