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Searched refs:S6_COLOR_WRITE_ENABLE (Results 1 – 12 of 12) sorted by relevance

/external/mesa3d/src/mesa/drivers/dri/i915/
Dintel_reg.h181 #define S6_COLOR_WRITE_ENABLE (1<<2) macro
Di915_vtbl.c679 dw |= S6_COLOR_WRITE_ENABLE; in i915_update_color_write_enable()
681 dw &= ~S6_COLOR_WRITE_ENABLE; in i915_update_color_write_enable()
Di915_state.c940 i915->state.Ctx[I915_CTXREG_LIS6] = (S6_COLOR_WRITE_ENABLE | in i915_init_packets()
/external/mesa3d/src/gallium/drivers/i915/
Di915_state_immediate.c167 LIS6 |= S6_COLOR_WRITE_ENABLE; in upload_S6()
Di915_reg.h434 #define S6_COLOR_WRITE_ENABLE (1<<2) macro
/external/igt-gpu-tools/lib/
Drendercopy_i915.c174 OUT_BATCH(S6_CBUF_BLEND_ENABLE | S6_COLOR_WRITE_ENABLE | in gen3_render_copyfunc()
Di915_reg.h437 #define S6_COLOR_WRITE_ENABLE (1<<2) macro
/external/igt-gpu-tools/tests/i915/
Dgen3_render_linear_blits.c189 *b++ = (S6_CBUF_BLEND_ENABLE | S6_COLOR_WRITE_ENABLE | in copy()
Dgen3_render_tiledy_blits.c189 *b++ = (S6_CBUF_BLEND_ENABLE | S6_COLOR_WRITE_ENABLE | in copy()
Dgen3_render_tiledx_blits.c189 *b++ = (S6_CBUF_BLEND_ENABLE | S6_COLOR_WRITE_ENABLE | in copy()
Dgen3_render_mixed_blits.c202 *b++ = (S6_CBUF_BLEND_ENABLE | S6_COLOR_WRITE_ENABLE | in copy()
Dgen3_mixed_blits.c215 *b++ = (S6_CBUF_BLEND_ENABLE | S6_COLOR_WRITE_ENABLE | in render_copy()