| /external/llvm-project/llvm/test/CodeGen/AMDGPU/GlobalISel/ |
| D | irtranslator-sat.ll | 92 ; CHECK: [[SADDSAT:%[0-9]+]]:_(s16) = G_SADDSAT [[TRUNC]], [[TRUNC1]]
93 ; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[SADDSAT]](s16)
109 ; CHECK: [[SADDSAT:%[0-9]+]]:_(s32) = G_SADDSAT [[COPY]], [[COPY1]]
110 ; CHECK: $vgpr0 = COPY [[SADDSAT]](s32)
129 ; CHECK: [[SADDSAT:%[0-9]+]]:_(s64) = G_SADDSAT [[MV]], [[MV1]]
130 ; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[SADDSAT]](s64)
151 ; CHECK: [[SADDSAT:%[0-9]+]]:_(<2 x s32>) = G_SADDSAT [[BUILD_VECTOR]], [[BUILD_VECTOR1]]
152 ; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[SADDSAT]](<2 x s32>)
|
| D | legalize-saddsat.mir | 62 ; GFX9: [[SADDSAT:%[0-9]+]]:_(s16) = G_SADDSAT [[SHL]], [[SHL1]]
63 ; GFX9: [[ASHR:%[0-9]+]]:_(s16) = G_ASHR [[SADDSAT]], [[C]](s16)
131 ; GFX9: [[SADDSAT:%[0-9]+]]:_(s16) = G_SADDSAT [[SHL]], [[SHL1]]
132 ; GFX9: [[ASHR:%[0-9]+]]:_(s16) = G_ASHR [[SADDSAT]], [[C]](s16)
273 ; GFX9: [[SADDSAT:%[0-9]+]]:_(<2 x s16>) = G_SADDSAT [[SHL]], [[SHL1]]
274 ; GFX9: [[ASHR:%[0-9]+]]:_(<2 x s16>) = G_ASHR [[SADDSAT]], [[BUILD_VECTOR_TRUNC2]](<2 x s16>)
349 ; GFX9: [[SADDSAT:%[0-9]+]]:_(s16) = G_SADDSAT [[TRUNC]], [[TRUNC1]]
350 ; GFX9: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[SADDSAT]](s16)
449 ; GFX9: [[SADDSAT:%[0-9]+]]:_(<2 x s16>) = G_SADDSAT [[COPY]], [[COPY1]]
450 ; GFX9: $vgpr0 = COPY [[SADDSAT]](<2 x s16>)
[all …]
|
| /external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 266 SADDSAT, UADDSAT, enumerator
|
| D | TargetLowering.h | 2257 case ISD::SADDSAT: in isCommutativeBinOp()
|
| /external/llvm-project/llvm/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 320 SADDSAT, enumerator
|
| D | TargetLowering.h | 2424 case ISD::SADDSAT: in isCommutativeBinOp()
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/ |
| D | X86TargetTransformInfo.cpp | 1926 { ISD::SADDSAT, MVT::v32i16, 1 }, in getIntrinsicInstrCost()
1927 { ISD::SADDSAT, MVT::v64i8, 1 }, in getIntrinsicInstrCost()
1987 { ISD::SADDSAT, MVT::v16i16, 1 }, in getIntrinsicInstrCost()
1988 { ISD::SADDSAT, MVT::v32i8, 1 }, in getIntrinsicInstrCost()
2024 { ISD::SADDSAT, MVT::v16i16, 4 }, // 2 x 128-bit Op + extract/insert in getIntrinsicInstrCost()
2025 { ISD::SADDSAT, MVT::v32i8, 4 }, // 2 x 128-bit Op + extract/insert in getIntrinsicInstrCost()
2100 { ISD::SADDSAT, MVT::v8i16, 1 }, in getIntrinsicInstrCost()
2101 { ISD::SADDSAT, MVT::v16i8, 1 }, in getIntrinsicInstrCost()
2177 ISD = ISD::SADDSAT; in getIntrinsicInstrCost()
|
| /external/llvm-project/llvm/lib/Target/X86/ |
| D | X86TargetTransformInfo.cpp | 2327 { ISD::SADDSAT, MVT::v32i16, 1 }, in getTypeBasedIntrinsicInstrCost()
2328 { ISD::SADDSAT, MVT::v64i8, 1 }, in getTypeBasedIntrinsicInstrCost()
2399 { ISD::SADDSAT, MVT::v32i16, 2 }, // FIXME: include split in getTypeBasedIntrinsicInstrCost()
2400 { ISD::SADDSAT, MVT::v64i8, 2 }, // FIXME: include split in getTypeBasedIntrinsicInstrCost()
2454 { ISD::SADDSAT, MVT::v16i16, 1 }, in getTypeBasedIntrinsicInstrCost()
2455 { ISD::SADDSAT, MVT::v32i8, 1 }, in getTypeBasedIntrinsicInstrCost()
2509 { ISD::SADDSAT, MVT::v16i16, 4 }, // 2 x 128-bit Op + extract/insert in getTypeBasedIntrinsicInstrCost()
2510 { ISD::SADDSAT, MVT::v32i8, 4 }, // 2 x 128-bit Op + extract/insert in getTypeBasedIntrinsicInstrCost()
2621 { ISD::SADDSAT, MVT::v8i16, 1 }, in getTypeBasedIntrinsicInstrCost()
2622 { ISD::SADDSAT, MVT::v16i8, 1 }, in getTypeBasedIntrinsicInstrCost()
[all …]
|
| /external/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| D | LegalizeVectorOps.cpp | 452 case ISD::SADDSAT: in LegalizeOp()
839 case ISD::SADDSAT: in Expand()
|
| D | SelectionDAGDumper.cpp | 311 case ISD::SADDSAT: return "saddsat"; in getOperationName()
|
| D | LegalizeIntegerTypes.cpp | 158 case ISD::SADDSAT: in PromoteIntegerResult()
759 case ISD::SADDSAT: in PromoteIntRes_ADDSUBSHLSAT()
801 unsigned AddOp = Opcode == ISD::SADDSAT ? ISD::ADD : ISD::SUB; in PromoteIntRes_ADDSUBSHLSAT()
2138 case ISD::SADDSAT: in ExpandIntegerResult()
|
| D | LegalizeVectorTypes.cpp | 128 case ISD::SADDSAT: in ScalarizeVectorResult()
996 case ISD::SADDSAT: in SplitVectorResult()
2888 case ISD::SADDSAT: in WidenVectorResult()
|
| D | LegalizeDAG.cpp | 1134 case ISD::SADDSAT: in LegalizeOp()
3543 case ISD::SADDSAT: in ExpandNode()
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/SelectionDAG/ |
| D | SelectionDAGDumper.cpp | 305 case ISD::SADDSAT: return "saddsat"; in getOperationName()
|
| D | LegalizeVectorOps.cpp | 455 case ISD::SADDSAT: in LegalizeOp()
949 case ISD::SADDSAT: in Expand()
|
| D | LegalizeIntegerTypes.cpp | 153 case ISD::SADDSAT: in PromoteIntegerResult()
694 case ISD::SADDSAT: in PromoteIntRes_ADDSUBSAT()
733 unsigned AddOp = Opcode == ISD::SADDSAT ? ISD::ADD : ISD::SUB; in PromoteIntRes_ADDSUBSAT()
1906 case ISD::SADDSAT: in ExpandIntegerResult()
|
| D | LegalizeVectorTypes.cpp | 125 case ISD::SADDSAT: in ScalarizeVectorResult()
935 case ISD::SADDSAT: in SplitVectorResult()
2728 case ISD::SADDSAT: in WidenVectorResult()
|
| D | LegalizeDAG.cpp | 1122 case ISD::SADDSAT: in LegalizeOp()
3410 case ISD::SADDSAT: in ExpandNode()
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/ |
| D | TargetLoweringBase.cpp | 653 setOperationAction(ISD::SADDSAT, VT, Expand); in initActions()
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/WebAssembly/ |
| D | WebAssemblyISelLowering.cpp | 128 for (auto Op : {ISD::SADDSAT, ISD::UADDSAT}) in WebAssemblyTargetLowering()
|
| /external/llvm-project/llvm/lib/CodeGen/ |
| D | TargetLoweringBase.cpp | 763 setOperationAction(ISD::SADDSAT, VT, Expand); in initActions()
|
| /external/llvm-project/llvm/lib/Target/WebAssembly/ |
| D | WebAssemblyISelLowering.cpp | 133 for (auto Op : {ISD::SADDSAT, ISD::UADDSAT}) in WebAssemblyTargetLowering()
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/ |
| D | ARMISelLowering.cpp | 219 for (auto Opcode : {ISD::SADDSAT, ISD::UADDSAT, ISD::SSUBSAT, ISD::USUBSAT}) in addTypeForNEON()
277 setOperationAction(ISD::SADDSAT, VT, Legal); in addMVEVectorTypes()
1048 setOperationAction(ISD::SADDSAT, MVT::i8, Custom); in ARMTargetLowering()
1050 setOperationAction(ISD::SADDSAT, MVT::i16, Custom); in ARMTargetLowering()
1054 setOperationAction(ISD::SADDSAT, MVT::i32, Legal); in ARMTargetLowering()
4558 bool IsAdd = Op->getOpcode() == ISD::SADDSAT; in LowerSADDSUBSAT()
9359 case ISD::SADDSAT: in LowerOperation()
9449 case ISD::SADDSAT: in ReplaceNodeResults()
|
| /external/llvm-project/llvm/lib/Target/ARM/ |
| D | ARMISelLowering.cpp | 221 for (auto Opcode : {ISD::SADDSAT, ISD::UADDSAT, ISD::SSUBSAT, ISD::USUBSAT}) in addTypeForNEON()
279 setOperationAction(ISD::SADDSAT, VT, Legal); in addMVEVectorTypes()
1099 setOperationAction(ISD::SADDSAT, MVT::i8, Custom); in ARMTargetLowering()
1101 setOperationAction(ISD::SADDSAT, MVT::i16, Custom); in ARMTargetLowering()
1105 setOperationAction(ISD::SADDSAT, MVT::i32, Legal); in ARMTargetLowering()
4836 bool IsAdd = Op->getOpcode() == ISD::SADDSAT; in LowerSADDSUBSAT()
9790 case ISD::SADDSAT: in LowerOperation()
9890 case ISD::SADDSAT: in ReplaceNodeResults()
|
| /external/llvm-project/llvm/lib/Target/AMDGPU/ |
| D | SIISelLowering.cpp | 498 setOperationAction(ISD::SADDSAT, MVT::i16, Legal); in SITargetLowering()
500 setOperationAction(ISD::SADDSAT, MVT::i32, Legal); in SITargetLowering()
724 setOperationAction(ISD::SADDSAT, MVT::v2i16, Legal); in SITargetLowering()
755 setOperationAction(ISD::SADDSAT, MVT::v4i16, Custom); in SITargetLowering()
4587 case ISD::SADDSAT: in LowerOperation()
|