| /external/harfbuzz_ng/src/ |
| D | hb-ot-shape-complex-hangul.cc | 106 #define SBase 0xAC00u macro
113 #define isCombinedS(u) (hb_in_range<hb_codepoint_t> ((u), SBase, SBase+SCount-1))
271 hb_codepoint_t s = SBase + (l - LBase) * NCount + (v - VBase) * TCount + tindex; in preprocess_text_hangul()
310 unsigned int lindex = (s - SBase) / NCount; in preprocess_text_hangul()
311 unsigned int nindex = (s - SBase) % NCount; in preprocess_text_hangul()
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| /external/python/cpython2/Modules/ |
| D | unicodedata.c | 486 #define SBase 0xAC00 macro
539 if (SBase <= code && code < (SBase+SCount)) { in nfd_nfkd()
540 int SIndex = code - SBase; in nfd_nfkd()
673 code = SBase + (LIndex*VCount+VIndex)*TCount; in nfc_nfkc()
912 if (SBase <= code && code < SBase+SCount) { in _getucname()
914 int SIndex = code - SBase; in _getucname()
1036 *code = SBase + (L*VCount+V)*TCount + T; in _getcode()
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| /external/python/cpython3/Modules/ |
| D | unicodedata.c | 482 #define SBase 0xAC00 macro
546 if (SBase <= code && code < (SBase+SCount)) { in nfd_nfkd()
547 int SIndex = code - SBase; in nfd_nfkd()
697 code = SBase + (LIndex*VCount+VIndex)*TCount; in nfc_nfkc()
1081 if (SBase <= code && code < SBase+SCount) { in _getucname()
1083 int SIndex = code - SBase; in _getucname()
1225 *code = SBase + (L*VCount+V)*TCount + T; in _getcode()
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| /external/icu/icu4j/main/tests/core/src/com/ibm/icu/dev/test/normalizer/ |
| D | NormalizerBuilder.java | 233 first = (char)(SBase + SIndex - TIndex); in buildDecompositionTables()
240 value = SIndex + SBase; in buildDecompositionTables()
251 SBase = 0xAC00, LBase = 0x1100, VBase = 0x1161, TBase = 0x11A7, field in NormalizerBuilder
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| /external/icu/android_icu4j/src/main/tests/android/icu/dev/test/normalizer/ |
| D | NormalizerBuilder.java | 234 first = (char)(SBase + SIndex - TIndex); in buildDecompositionTables()
241 value = SIndex + SBase; in buildDecompositionTables()
252 SBase = 0xAC00, LBase = 0x1100, VBase = 0x1161, TBase = 0x11A7, field in NormalizerBuilder
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| /external/llvm/lib/Target/AMDGPU/ |
| D | AMDGPUISelDAGToDAG.cpp | 124 bool SelectSMRD(SDValue Addr, SDValue &SBase, SDValue &Offset,
126 bool SelectSMRDImm(SDValue Addr, SDValue &SBase, SDValue &Offset) const;
127 bool SelectSMRDImm32(SDValue Addr, SDValue &SBase, SDValue &Offset) const;
128 bool SelectSMRDSgpr(SDValue Addr, SDValue &SBase, SDValue &Offset) const;
1123 bool AMDGPUDAGToDAGISel::SelectSMRD(SDValue Addr, SDValue &SBase, in SelectSMRD() argument
1132 SBase = N0; in SelectSMRD()
1136 SBase = Addr; in SelectSMRD()
1142 bool AMDGPUDAGToDAGISel::SelectSMRDImm(SDValue Addr, SDValue &SBase, in SelectSMRDImm() argument
1145 return SelectSMRD(Addr, SBase, Offset, Imm) && Imm; in SelectSMRDImm()
1148 bool AMDGPUDAGToDAGISel::SelectSMRDImm32(SDValue Addr, SDValue &SBase, in SelectSMRDImm32() argument
[all …]
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| D | SIInstrInfo.cpp | 2199 MachineOperand *SBase = getNamedOperand(MI, AMDGPU::OpName::sbase); in legalizeOperandsSMRD() local
2200 if (SBase && !RI.isSGPRClass(MRI.getRegClass(SBase->getReg()))) { in legalizeOperandsSMRD()
2201 unsigned SGPR = readlaneVGPRToSGPR(SBase->getReg(), MI, MRI); in legalizeOperandsSMRD()
2202 SBase->setReg(SGPR); in legalizeOperandsSMRD()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
| D | AMDGPUISelDAGToDAG.cpp | 245 bool SelectSMRD(SDValue Addr, SDValue &SBase, SDValue &Offset,
247 bool SelectSMRDImm(SDValue Addr, SDValue &SBase, SDValue &Offset) const;
248 bool SelectSMRDImm32(SDValue Addr, SDValue &SBase, SDValue &Offset) const;
249 bool SelectSMRDSgpr(SDValue Addr, SDValue &SBase, SDValue &Offset) const;
1821 bool AMDGPUDAGToDAGISel::SelectSMRD(SDValue Addr, SDValue &SBase, in SelectSMRD() argument
1834 SBase = Expand32BitAddress(N0); in SelectSMRD()
1838 SBase = Expand32BitAddress(Addr); in SelectSMRD()
1844 bool AMDGPUDAGToDAGISel::SelectSMRDImm(SDValue Addr, SDValue &SBase, in SelectSMRDImm() argument
1847 return SelectSMRD(Addr, SBase, Offset, Imm) && Imm; in SelectSMRDImm()
1850 bool AMDGPUDAGToDAGISel::SelectSMRDImm32(SDValue Addr, SDValue &SBase, in SelectSMRDImm32() argument
[all …]
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| D | SIInstrInfo.cpp | 4269 MachineOperand *SBase = getNamedOperand(MI, AMDGPU::OpName::sbase); in legalizeOperandsSMRD() local
4270 if (SBase && !RI.isSGPRClass(MRI.getRegClass(SBase->getReg()))) { in legalizeOperandsSMRD()
4271 unsigned SGPR = readlaneVGPRToSGPR(SBase->getReg(), MI, MRI); in legalizeOperandsSMRD()
4272 SBase->setReg(SGPR); in legalizeOperandsSMRD()
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| /external/llvm-project/llvm/lib/Target/AMDGPU/ |
| D | AMDGPUISelDAGToDAG.cpp | 253 bool SelectSMRD(SDValue Addr, SDValue &SBase, SDValue &Offset,
255 bool SelectSMRDImm(SDValue Addr, SDValue &SBase, SDValue &Offset) const;
256 bool SelectSMRDImm32(SDValue Addr, SDValue &SBase, SDValue &Offset) const;
257 bool SelectSMRDSgpr(SDValue Addr, SDValue &SBase, SDValue &Offset) const;
2030 bool AMDGPUDAGToDAGISel::SelectSMRD(SDValue Addr, SDValue &SBase, in SelectSMRD() argument
2049 SBase = Expand32BitAddress(N0); in SelectSMRD()
2054 SBase = Expand32BitAddress(Addr); in SelectSMRD()
2060 bool AMDGPUDAGToDAGISel::SelectSMRDImm(SDValue Addr, SDValue &SBase, in SelectSMRDImm() argument
2063 return SelectSMRD(Addr, SBase, Offset, Imm) && Imm; in SelectSMRDImm()
2066 bool AMDGPUDAGToDAGISel::SelectSMRDImm32(SDValue Addr, SDValue &SBase, in SelectSMRDImm32() argument
[all …]
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| D | SILoadStoreOptimizer.cpp | 108 bool SBase = false; member
485 Result.SBase = true; in getRegs()
562 if (Regs.SBase) in setMI()
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| D | SIInstrInfo.cpp | 4758 MachineOperand *SBase = getNamedOperand(MI, AMDGPU::OpName::sbase); in legalizeOperandsSMRD() local
4759 if (SBase && !RI.isSGPRClass(MRI.getRegClass(SBase->getReg()))) { in legalizeOperandsSMRD()
4760 Register SGPR = readlaneVGPRToSGPR(SBase->getReg(), MI, MRI); in legalizeOperandsSMRD()
4761 SBase->setReg(SGPR); in legalizeOperandsSMRD()
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| /external/llvm-project/llvm/test/Demangle/ |
| D | ms-operators.test | 95 ??SBase@@QEAAHXZ
|