/external/llvm-project/llvm/test/CodeGen/AVR/ |
D | cttz.ll | 14 ; CHECK: mov [[SCRATCH:r[0-9]+]], {{.*}}[[RESULT]] 15 ; CHECK: dec {{.*}}[[SCRATCH]] 17 ; CHECK: and {{.*}}[[RESULT]], {{.*}}[[SCRATCH]] 18 ; CHECK: mov {{.*}}[[SCRATCH]], {{.*}}[[RESULT]] 19 ; CHECK: lsr {{.*}}[[SCRATCH]] 20 ; CHECK: andi {{.*}}[[SCRATCH]], 85 21 ; CHECK: sub {{.*}}[[RESULT]], {{.*}}[[SCRATCH]] 22 ; CHECK: mov {{.*}}[[SCRATCH]], {{.*}}[[RESULT]] 23 ; CHECK: andi {{.*}}[[SCRATCH]], 51 27 ; CHECK: add {{.*}}[[RESULT]], {{.*}}[[SCRATCH]] [all …]
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D | ctlz.ll | 15 ; CHECK: mov [[SCRATCH:r[0-9]+]], {{.*}}[[RESULT]] 16 ; CHECK: lsr {{.*}}[[SCRATCH]] 17 ; CHECK: or {{.*}}[[SCRATCH]], {{.*}}[[RESULT]] 18 ; CHECK: mov {{.*}}[[RESULT]], {{.*}}[[SCRATCH]] 21 ; CHECK: or {{.*}}[[RESULT]], {{.*}}[[SCRATCH]] 22 ; CHECK: mov {{.*}}[[SCRATCH]], {{.*}}[[RESULT]] 23 ; CHECK: lsr {{.*}}[[SCRATCH]] 24 ; CHECK: lsr {{.*}}[[SCRATCH]] 25 ; CHECK: lsr {{.*}}[[SCRATCH]] 26 ; CHECK: lsr {{.*}}[[SCRATCH]] [all …]
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D | ctpop.ll | 12 ; CHECK: mov [[SCRATCH:r[0-9]+]], [[RESULT:r[0-9]+]] 13 ; CHECK: lsr {{.*}}[[SCRATCH]] 14 ; CHECK: andi {{.*}}[[SCRATCH]], 85 15 ; CHECK: sub {{.*}}[[RESULT]], {{.*}}[[SCRATCH]] 16 ; CHECK: mov {{.*}}[[SCRATCH]], {{.*}}[[RESULT]] 17 ; CHECK: andi {{.*}}[[SCRATCH]], 51 21 ; CHECK: add {{.*}}[[RESULT]], {{.*}}[[SCRATCH]] 22 ; CHECK: mov {{.*}}[[SCRATCH]], {{.*}}[[RESULT]] 23 ; CHECK: lsr {{.*}}[[SCRATCH]] 24 ; CHECK: lsr {{.*}}[[SCRATCH]] [all …]
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/external/igt-gpu-tools/tests/ |
D | prime_busy.c | 46 #define SCRATCH 0 in busy() macro 65 obj[SCRATCH].handle = gem_create(fd, 4096); in busy() 74 pfd[SCRATCH].fd = prime_handle_to_fd(fd, obj[SCRATCH].handle); in busy() 84 store[count].target_handle = obj[SCRATCH].handle; in busy() 136 pfd[SCRATCH].fd = prime_handle_to_fd(fd, obj[SCRATCH].handle); in busy() 140 igt_assert(prime_busy(&pfd[SCRATCH], false)); in busy() 141 igt_assert(prime_busy(&pfd[SCRATCH], true)); in busy() 162 igt_assert(!prime_busy(&pfd[SCRATCH], true)); in busy() 165 batch = gem_mmap__wc(fd, obj[SCRATCH].handle, 0, 4096, PROT_READ); in busy() 171 gem_close(fd, obj[SCRATCH].handle); in busy() [all …]
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/external/llvm-project/llvm/test/CodeGen/AVR/pseudo/ |
D | LDWRdPtr-same-src-dst.mir | 21 ; CHECK: ld [[SCRATCH:r[0-9]+]], Z 22 ; CHECK-NEXT: push [[SCRATCH]] 23 ; CHECK-NEXT: ldd [[SCRATCH]], Z+1 24 ; CHECK-NEXT: mov r31, [[SCRATCH]]
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/external/llvm-project/llvm/test/CodeGen/AArch64/ |
D | framelayout-scavengingslot.mir | 8 # CHECK: STRXui killed $[[SCRATCH:x[0-9]+]], $sp, 3 9 # CHECK-NEXT: $[[SCRATCH]] = ADDXri $sp, 40, 0 10 # CHECK-NEXT: STRXui $x0, killed $[[SCRATCH]], 4095 11 # CHECK-NEXT: $[[SCRATCH]] = LDRXui $sp, 3
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D | framelayout-sve-scavengingslot.mir | 10 # CHECK: STRXui killed $[[SCRATCH:x[0-9]+]], $sp, 1 11 # CHECK-NEXT: $[[SCRATCH]] = ADDVL_XXI $fp, -1 12 # CHECK-NEXT: STRXui $x0, killed $[[SCRATCH]], 0
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D | framelayout-sve.mir | 59 # CHECK-NEXT: $sp = frame-setup STRXpre killed $[[SCRATCH:[a-z0-9]+]], $sp, -16 66 # CHECK-NEXT: $sp, $[[SCRATCH]] = frame-destroy LDRXpost $sp, 16 97 # CHECK-NEXT: $sp = frame-setup STRXpre killed $[[SCRATCH:[a-z0-9]+]], $sp, -32 108 # CHECK-NEXT: $sp, $[[SCRATCH]] = frame-destroy LDRXpost $sp, 32 186 # CHECK-NEXT: $sp = frame-setup STRXpre killed $[[SCRATCH:[a-z0-9]+]], $sp, -16 200 # CHECK-NEXT: $sp, $[[SCRATCH]] = frame-destroy LDRXpost $sp, 16 300 # CHECK-NEXT: $sp = frame-setup STRXpre killed $[[SCRATCH:[a-z0-9]+]], $sp, -16 310 # CHECK-NEXT: $sp, $[[SCRATCH]] = frame-destroy LDRXpost $sp, 16 350 # CHECK-NEXT: $sp = frame-setup STRXpre killed $[[SCRATCH:[a-z0-9]+]], $sp, -16 377 # CHECK-NEXT: $sp, $[[SCRATCH]] = frame-destroy LDRXpost $sp, 16 [all …]
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/external/igt-gpu-tools/tests/i915/ |
D | gem_exec_async.c | 87 #define SCRATCH 0 in one() macro 101 obj[SCRATCH].handle = gem_create(fd, 4096); in one() 153 store_dword(fd, other, obj[SCRATCH].handle, 4*i, i); in one() 161 batch = gem_mmap__wc(fd, obj[SCRATCH].handle, 0, 4096, PROT_READ); in one() 166 gem_set_domain(fd, obj[SCRATCH].handle, in one() 168 gem_close(fd, obj[SCRATCH].handle); in one()
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D | gem_busy.c | 166 #define SCRATCH 0 in one() macro 185 obj[SCRATCH].handle = gem_create(fd, 4096); in one() 198 store[count].target_handle = obj[SCRATCH].handle; in one() 248 __gem_busy(fd, obj[SCRATCH].handle, &read[SCRATCH], &write[SCRATCH]); in one() 274 igt_assert_eq(write[SCRATCH], 1 + uabi); in one() 275 igt_assert_eq_u32(read[SCRATCH], 1 << uabi); in one() 284 igt_assert(!gem_busy(fd, obj[SCRATCH].handle)); in one() 287 batch = gem_mmap__wc(fd, obj[SCRATCH].handle, 0, 4096, PROT_READ); in one() 293 gem_close(fd, obj[SCRATCH].handle); in one()
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D | gem_exec_capture.c | 68 #define SCRATCH 0 in __capture1() macro 78 obj[SCRATCH].handle = gem_create(fd, 4096); in __capture1() 95 reloc[1].target_handle = obj[SCRATCH].handle; /* breadcrumb */ in __capture1() 102 seqno = gem_mmap__wc(fd, obj[SCRATCH].handle, 0, 4096, PROT_READ); in __capture1() 103 gem_set_domain(fd, obj[SCRATCH].handle, in __capture1() 157 igt_assert(gem_bo_busy(fd, obj[SCRATCH].handle)); in __capture1() 168 gem_close(fd, obj[SCRATCH].handle); in __capture1()
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/external/llvm/test/CodeGen/ARM/ |
D | 2014-02-21-byval-reg-split-alignment.ll | 19 ; CHECK: add [[SCRATCH:r[0-9]+]], sp, #12 20 ; CHECK: stm [[SCRATCH]], {r1, r2, r3} 54 ; CHECK: add [[SCRATCH:r[0-9]+]], sp, #8 55 ; CHECK: stm [[SCRATCH]], {r0, r1, r2} 91 ; CHECK: add [[SCRATCH:r[0-9]+]], sp, #8 92 ; CHECK: stm [[SCRATCH]], {r0, r1, r2, r3}
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/external/llvm-project/llvm/test/CodeGen/ARM/ |
D | 2014-02-21-byval-reg-split-alignment.ll | 19 ; CHECK: add [[SCRATCH:r[0-9]+]], sp, #12 20 ; CHECK: stm [[SCRATCH]], {r1, r2, r3} 54 ; CHECK: add [[SCRATCH:r[0-9]+]], sp, #8 55 ; CHECK: stm [[SCRATCH]], {r0, r1, r2} 91 ; CHECK: add [[SCRATCH:r[0-9]+]], sp, #8 92 ; CHECK: stm [[SCRATCH]], {r0, r1, r2, r3}
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/external/mesa3d/src/gallium/drivers/nouveau/nvc0/mme/ |
D | com9097.mme | 241 * SCRATCH[0] = saved VB_ELEMENT_BASE 242 * SCRATCH[1] = saved VB_INSTANCE_BASE 248 send $r6 /* SCRATCH[0] = VB_ELEMENT_BASE */ 249 send $r7 /* SCRATCH[1] = VB_INSTANCE_BASE */ 353 * SCRATCH[0] = saved VB_ELEMENT_BASE 354 * SCRATCH[1] = saved VB_INSTANCE_BASE 355 * SCRATCH[2] = draws left 361 send $r6 /* SCRATCH[0] = VB_ELEMENT_BASE */ 362 send $r7 /* SCRATCH[1] = VB_INSTANCE_BASE */ 439 * SCRATCH[0] = VB_INSTANCE_BASE [all …]
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/external/igt-gpu-tools/lib/ |
D | igt_dummyload.c | 75 #define SCRATCH 0 in emit_recursive_batch() macro 127 obj[SCRATCH].handle = opts->dependency; in emit_recursive_batch() 129 r->target_handle = obj[SCRATCH].handle; in emit_recursive_batch() 147 obj[SCRATCH].handle = spin->poll_handle; in emit_recursive_batch() 163 r->target_handle = obj[SCRATCH].handle; in emit_recursive_batch()
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/external/llvm-project/llvm/test/CodeGen/PowerPC/ |
D | aix64-cc-byval.ll | 99 ; CHECK: renamable $x[[SCRATCH:[0-9]+]] = COPY $x3 101 ; CHECK-DAG: STD killed renamable $x[[SCRATCH]], 0, %fixed-stack.0 :: (store 8 into %fixed-sta… 106 ; ASM: mr [[SCRATCH:[0-9]+]], 3 108 ; ASM-DAG: std [[SCRATCH]], 48(1)
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/external/libavc/encoder/ |
D | irc_mem_req_and_acq.h | 73 SCRATCH = 0, enumerator
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D | ih264e_rc_mem_interface.h | 73 SCRATCH = 0, enumerator
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/external/libhevc/encoder/ |
D | mem_req_and_acq.h | 41 SCRATCH = 0, enumerator
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/external/mesa3d/src/amd/compiler/ |
D | aco_insert_NOPs.cpp | 397 } else if (instr->isVMEM() || instr->isFlatOrGlobal() || instr->format == Format::SCRATCH) { in handle_instruction_gfx6() 409 … bool lds_scratch_global = (instr->format == Format::SCRATCH || instr->format == Format::GLOBAL) && in handle_instruction_gfx6() 492 } else if (instr->isVMEM() || instr->isFlatOrGlobal() || instr->format == Format::SCRATCH) { in handle_instruction_gfx6() 504 bool consider_flat = (instr->isFlatOrGlobal() || instr->format == Format::SCRATCH) && in handle_instruction_gfx6() 598 instr->format == Format::SCRATCH || instr->format == Format::DS) { in handle_instruction_gfx10() 715 if (instr->isVMEM() || instr->format == Format::GLOBAL || instr->format == Format::SCRATCH) { in handle_instruction_gfx10()
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D | README-ISA.md | 166 VMEM/FLAT/GLOBAL/SCRATCH/DS instruction reads an SGPR (or EXEC, or M0). 200 GLOBAL and SCRATCH are unaffected. 225 VMEM/GLOBAL/SCRATCH instruction, then a branch, then a DS instruction, 226 or vice versa: DS instruction, then a branch, then a VMEM/GLOBAL/SCRATCH instruction.
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D | aco_opcodes.py | 48 SCRATCH = 15 variable in Format 137 elif self in [Format.FLAT, Format.GLOBAL, Format.SCRATCH]: 1603 SCRATCH = { variable 1628 for (gfx8, gfx10, name) in SCRATCH: 1629 opcode(name, -1, gfx8, gfx10, Format.SCRATCH)
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D | aco_form_hard_clauses.cpp | 81 } else if (instr->format == Format::SCRATCH || instr->format == Format::GLOBAL) { in form_hard_clauses()
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/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
D | SIMemoryLegalizer.cpp | 85 SCRATCH = 1u << 2, enumerator 90 FLAT = GLOBAL | LDS | SCRATCH, 93 ATOMIC = GLOBAL | LDS | SCRATCH | GDS, 96 ALL = GLOBAL | LDS | SCRATCH | GDS | OTHER, 505 return SIAtomicAddrSpace::SCRATCH; in toSIAtomicAddrSpace()
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/external/llvm-project/llvm/lib/Target/AMDGPU/ |
D | SIMemoryLegalizer.cpp | 89 SCRATCH = 1u << 2, enumerator 94 FLAT = GLOBAL | LDS | SCRATCH, 97 ATOMIC = GLOBAL | LDS | SCRATCH | GDS, 100 ALL = GLOBAL | LDS | SCRATCH | GDS | OTHER, 531 return SIAtomicAddrSpace::SCRATCH; in toSIAtomicAddrSpace()
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