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Searched refs:SCRATCH_RSRC_DWORD0 (Results 1 – 25 of 28) sorted by relevance

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/external/llvm/test/MC/AMDGPU/
Dreloc.s10 s_mov_b32 s0, SCRATCH_RSRC_DWORD0
16 .globl SCRATCH_RSRC_DWORD0 symbol
/external/llvm-project/llvm/test/MC/AMDGPU/
Dreloc.s21 s_mov_b32 s0, SCRATCH_RSRC_DWORD0
35 .globl SCRATCH_RSRC_DWORD0 symbol
/external/llvm/test/CodeGen/AMDGPU/
Dlarge-alloca-graphics.ll5 ; GCN-DAG: s_mov_b32 s8, SCRATCH_RSRC_DWORD0
26 ; GCN-DAG: s_mov_b32 s8, SCRATCH_RSRC_DWORD0
Dlarge-alloca-compute.ll10 ; GCN-DAG: s_mov_b32 s{{[0-9]+}}, SCRATCH_RSRC_DWORD0
11 ; GCN-DAG: ; fixup A - offset: 4, value: SCRATCH_RSRC_DWORD0
Dpromote-alloca-stored-pointer-value.ll28 ; GCN-DAG: s_mov_b32 s{{[0-9]+}}, SCRATCH_RSRC_DWORD0
43 ; GCN-DAG: s_mov_b32 s{{[0-9]+}}, SCRATCH_RSRC_DWORD0
Dtarget-cpu.ll93 ; CHECK: SCRATCH_RSRC_DWORD0
Dvgpr-spill-emergency-stack-slot.ll16 ; GCN-DAG: s_mov_b32 s16, SCRATCH_RSRC_DWORD0
Dvgpr-spill-emergency-stack-slot-compute.ll23 ; GCNMESA-DAG: s_mov_b32 s12, SCRATCH_RSRC_DWORD0
/external/llvm-project/llvm/test/CodeGen/AMDGPU/
Dspill-agpr.ll5 ; A2M-DAG: s_mov_b32 s{{[0-9]+}}, SCRATCH_RSRC_DWORD0
34 ; A2M-DAG: s_mov_b32 s{{[0-9]+}}, SCRATCH_RSRC_DWORD0
63 ; A2M-DAG: s_mov_b32 s{{[0-9]+}}, SCRATCH_RSRC_DWORD0
85 ; A2M-DAG: s_mov_b32 s{{[0-9]+}}, SCRATCH_RSRC_DWORD0
Dlarge-alloca-graphics.ll6 ; GCN-DAG: s_mov_b32 s4, SCRATCH_RSRC_DWORD0
32 ; GCN-DAG: s_mov_b32 s4, SCRATCH_RSRC_DWORD0
Dlarge-alloca-compute.ll12 ; GCN-DAG: s_mov_b32 s{{[0-9]+}}, SCRATCH_RSRC_DWORD0
13 ; GCN-DAG: ; fixup A - offset: 4, value: SCRATCH_RSRC_DWORD0
Dpromote-alloca-stored-pointer-value.ll28 ; GCN-DAG: s_mov_b32 s{{[0-9]+}}, SCRATCH_RSRC_DWORD0
43 ; GCN-DAG: s_mov_b32 s{{[0-9]+}}, SCRATCH_RSRC_DWORD0
Dspill-vgpr-to-agpr.ll5 ; GFX900-DAG: s_mov_b32 s{{[0-9]+}}, SCRATCH_RSRC_DWORD0
60 ; GFX908-DAG: s_mov_b32 s{{[0-9]+}}, SCRATCH_RSRC_DWORD0
113 ; GCN-DAG: s_mov_b32 s{{[0-9]+}}, SCRATCH_RSRC_DWORD0
167 ; GCN-DAG: s_mov_b32 s{{[0-9]+}}, SCRATCH_RSRC_DWORD0
188 ; GFX900-DAG: s_mov_b32 s{{[0-9]+}}, SCRATCH_RSRC_DWORD0
239 ; GFX900-DAG: s_mov_b32 s{{[0-9]+}}, SCRATCH_RSRC_DWORD0
Dspill-special-sgpr.mir42 ; GFX9: $sgpr12 = S_MOV_B32 &SCRATCH_RSRC_DWORD0, implicit-def $sgpr12_sgpr13_sgpr14_sgpr15
73 ; GFX10: $sgpr96 = S_MOV_B32 &SCRATCH_RSRC_DWORD0, implicit-def $sgpr96_sgpr97_sgpr98_sgpr99
Didot8u.ll14 ; GFX7-NEXT: s_mov_b32 s24, SCRATCH_RSRC_DWORD0
67 ; GFX8-NEXT: s_mov_b32 s20, SCRATCH_RSRC_DWORD0
120 ; GFX9-NEXT: s_mov_b32 s20, SCRATCH_RSRC_DWORD0
172 ; GFX9-DL-NEXT: s_mov_b32 s8, SCRATCH_RSRC_DWORD0
192 ; GFX10-DL-NEXT: s_mov_b32 s8, SCRATCH_RSRC_DWORD0
284 ; GFX7-NEXT: s_mov_b32 s20, SCRATCH_RSRC_DWORD0
339 ; GFX8-NEXT: s_mov_b32 s16, SCRATCH_RSRC_DWORD0
394 ; GFX9-NEXT: s_mov_b32 s20, SCRATCH_RSRC_DWORD0
447 ; GFX9-DL-NEXT: s_mov_b32 s20, SCRATCH_RSRC_DWORD0
499 ; GFX10-DL-NEXT: s_mov_b32 s8, SCRATCH_RSRC_DWORD0
[all …]
Didot8s.ll16 ; GFX7-NEXT: s_mov_b32 s24, SCRATCH_RSRC_DWORD0
67 ; GFX8-NEXT: s_mov_b32 s20, SCRATCH_RSRC_DWORD0
120 ; GFX9-NEXT: s_mov_b32 s20, SCRATCH_RSRC_DWORD0
174 ; GFX9-DL-NEXT: s_mov_b32 s8, SCRATCH_RSRC_DWORD0
194 ; GFX10-DL-NEXT: s_mov_b32 s8, SCRATCH_RSRC_DWORD0
286 ; GFX7-NEXT: s_mov_b32 s24, SCRATCH_RSRC_DWORD0
358 ; GFX8-NEXT: s_mov_b32 s16, SCRATCH_RSRC_DWORD0
416 ; GFX9-NEXT: s_mov_b32 s20, SCRATCH_RSRC_DWORD0
472 ; GFX9-DL-NEXT: s_mov_b32 s20, SCRATCH_RSRC_DWORD0
527 ; GFX10-DL-NEXT: s_mov_b32 s12, SCRATCH_RSRC_DWORD0
[all …]
Dscratch-simple.ll12 ; RELS: R_AMDGPU_ABS32_LO SCRATCH_RSRC_DWORD0 0x0
52 ; MUBUF-DAG: s_mov_b32 s0, SCRATCH_RSRC_DWORD0
117 ; MUBUF-DAG: s_mov_b32 s0, SCRATCH_RSRC_DWORD0
168 ; MUBUF-DAG: s_mov_b32 s0, SCRATCH_RSRC_DWORD0
193 ; SIVI: s_mov_b32 s0, SCRATCH_RSRC_DWORD0
198 ; GFX9_10-MUBUF: s_mov_b32 s0, SCRATCH_RSRC_DWORD0
243 ; SIVI: s_mov_b32 s0, SCRATCH_RSRC_DWORD0
247 ; GFX9_10-MUBUF: s_mov_b32 s0, SCRATCH_RSRC_DWORD0
296 ; MUBUF: s_mov_b32 s8, SCRATCH_RSRC_DWORD0
350 ; MUBUF: s_mov_b32 s8, SCRATCH_RSRC_DWORD0
Dmemory-legalizer-multiple-mem-operands-atomics.mir20 $sgpr8 = S_MOV_B32 &SCRATCH_RSRC_DWORD0, implicit-def $sgpr8_sgpr9_sgpr10_sgpr11
Dsi-spill-sgpr-stack.ll5 ; ALL: s_mov_b32 s[[LO:[0-9]+]], SCRATCH_RSRC_DWORD0
Dmemory-legalizer-private-nontemporal.ll11 ; GFX6-NEXT: s_mov_b32 s8, SCRATCH_RSRC_DWORD0
106 ; GFX6-NEXT: s_mov_b32 s8, SCRATCH_RSRC_DWORD0
206 ; GFX6-NEXT: s_mov_b32 s4, SCRATCH_RSRC_DWORD0
299 ; GFX6-NEXT: s_mov_b32 s4, SCRATCH_RSRC_DWORD0
Dtarget-cpu.ll92 ; CHECK: SCRATCH_RSRC_DWORD0
Dmemory-legalizer-multiple-mem-operands-nontemporal-2.mir94 $sgpr8 = S_MOV_B32 &SCRATCH_RSRC_DWORD0, implicit-def $sgpr8_sgpr9_sgpr10_sgpr11
Dmemory-legalizer-multiple-mem-operands-nontemporal-1.mir114 $sgpr8 = S_MOV_B32 &SCRATCH_RSRC_DWORD0, implicit-def $sgpr8_sgpr9_sgpr10_sgpr11
Dstack-pointer-offset-relative-frameindex.ll20 ; MUBUF-NEXT: s_mov_b32 s36, SCRATCH_RSRC_DWORD0
Dvgpr-spill-emergency-stack-slot.ll17 ; GCN-DAG: s_mov_b32 s[[DESC0:[0-9]+]], SCRATCH_RSRC_DWORD0

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