| /external/llvm-project/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/ |
| D | store.mir | 81 ; MIPS32FP32: SDC1 [[COPY]], [[COPY1]], 0 :: (store 8 into %ir.ptr)
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| D | load_store_fold.mir | 156 ; MIPS32: SDC1 [[COPY]], [[COPY1]], -80 :: (store 8)
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| /external/llvm-project/llvm/lib/Target/Mips/MCTargetDesc/ |
| D | MipsNaClELFStreamer.cpp | 239 case Mips::SDC1: in isBasePlusOffsetMemoryAccess()
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| /external/llvm/lib/Target/Mips/MCTargetDesc/ |
| D | MipsNaClELFStreamer.cpp | 231 case Mips::SDC1: in isBasePlusOffsetMemoryAccess()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/MCTargetDesc/ |
| D | MipsNaClELFStreamer.cpp | 239 case Mips::SDC1: in isBasePlusOffsetMemoryAccess()
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| /external/llvm/lib/Target/Mips/ |
| D | MipsSEInstrInfo.cpp | 68 (Opc == Mips::SWC1) || (Opc == Mips::SDC1) || (Opc == Mips::SDC164)) { in isStoreToStackSlot()
207 Opc = Mips::SDC1; in storeRegToStack()
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| D | MipsInstrFPU.td | 424 def SDC1 : MMRel, SW_FT<"sdc1", AFGR64Opnd, mem_simm16, II_SDC1, store>,
654 def : StoreRegImmPat<SDC1, f64>, FGR_32;
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| D | MipsFastISel.cpp | 802 Opc = Mips::SDC1; in emitStore()
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/ |
| D | MipsSEInstrInfo.cpp | 72 (Opc == Mips::SWC1) || (Opc == Mips::SDC1) || (Opc == Mips::SDC164)) { in isStoreToStackSlot()
269 Opc = Mips::SDC1; in storeRegToStack()
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| D | MipsInstrFPU.td | 586 def SDC1 : MMRel, SW_FT<"sdc1", AFGR64Opnd, mem_simm16, II_SDC1, store>,
809 <"s.d $fd, $addr", (SDC1 AFGR64Opnd:$fd, mem_simm16:$addr), 0>,
978 def : StoreRegImmPat<SDC1, f64>, ISA_MIPS1, FGR_32;
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| D | MipsInstructionSelector.cpp | 226 return isStore ? Mips::SDC1 : Mips::LDC1; in selectLoadStoreOpCode()
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| D | MipsScheduleP5600.td | 578 def : InstRW<[P5600WriteStoreFPUS], (instrs SDC1, SDC164, SDXC1, SDXC164,
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| D | MipsFastISel.cpp | 837 Opc = Mips::SDC1; in emitStore()
|
| /external/llvm-project/llvm/lib/Target/Mips/ |
| D | MipsSEInstrInfo.cpp | 72 (Opc == Mips::SWC1) || (Opc == Mips::SDC1) || (Opc == Mips::SDC164)) { in isStoreToStackSlot()
269 Opc = Mips::SDC1; in storeRegToStack()
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| D | MipsInstrFPU.td | 619 def SDC1 : MMRel, SW_FT<"sdc1", AFGR64Opnd, mem_simm16, II_SDC1, store>,
842 <"s.d $fd, $addr", (SDC1 AFGR64Opnd:$fd, mem_simm16:$addr), 0>,
1011 def : StoreRegImmPat<SDC1, f64>, ISA_MIPS1, FGR_32;
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| D | MipsInstructionSelector.cpp | 232 return isStore ? Mips::SDC1 : Mips::LDC1; in selectLoadStoreOpCode()
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| D | MipsScheduleP5600.td | 579 def : InstRW<[P5600WriteStoreFPUS], (instrs SDC1, SDC164, SDXC1, SDXC164,
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| D | MipsFastISel.cpp | 836 Opc = Mips::SDC1; in emitStore()
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| /external/llvm-project/llvm/test/MC/Mips/ |
| D | mips64-expansions.s | 473 # LW/SW and LDC1/SDC1 of symbol address, done by MipsAsmParser::expandMemInst():
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| D | target-soft-float.s | 315 # FIXME: SDC1 is correctly rejected but the wrong error message is emitted.
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| D | mips-expansions.s | 54 # LW/SW and LDC1/SDC1 of symbol address, done by MipsAsmParser::expandMemInst():
|
| /external/pcre/dist2/src/sljit/ |
| D | sljitNativeMIPS_32.c | 515 ins = SDC1 | S(SLJIT_SP) | FT(float_arg_count) | IMM(offsets[arg_count]); in call_with_args()
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| D | sljitNativeMIPS_common.c | 236 #define SDC1 (HI(61)) macro
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| /external/llvm/test/MC/Mips/ |
| D | mips-expansions.s | 16 # LW/SW and LDC1/SDC1 of symbol address, done by MipsAsmParser::expandMemInst():
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| D | target-soft-float.s | 315 # FIXME: SDC1 is correctly rejected but the wrong error message is emitted.
|