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Searched refs:SDTCisSubVecOfVec (Results 1 – 11 of 11) sorted by relevance

/external/llvm/include/llvm/Target/
DTargetSelectionDAG.td64 /// SDTCisSubVecOfVec - This indicates that ThisOp is a vector type
66 class SDTCisSubVecOfVec<int ThisOp, int OtherOp>
245 SDTCisSubVecOfVec<0,1>, SDTCisInt<2>
248 SDTCisSubVecOfVec<2, 1>, SDTCisSameAs<0,1>, SDTCisInt<3>
555 SDTypeProfile<1, 2, [SDTCisSubVecOfVec<1, 0>, SDTCisSameAs<1, 2>]>,[]>;
/external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/Target/
DTargetSelectionDAG.td63 /// SDTCisSubVecOfVec - This indicates that ThisOp is a vector type
65 class SDTCisSubVecOfVec<int ThisOp, int OtherOp>
250 SDTCisSubVecOfVec<0,1>, SDTCisInt<2>
253 SDTCisSubVecOfVec<2, 1>, SDTCisSameAs<0,1>, SDTCisInt<3>
646 SDTypeProfile<1, 2, [SDTCisSubVecOfVec<1, 0>, SDTCisSameAs<1, 2>]>,[]>;
/external/llvm-project/llvm/include/llvm/Target/
DTargetSelectionDAG.td63 /// SDTCisSubVecOfVec - This indicates that ThisOp is a vector type
65 class SDTCisSubVecOfVec<int ThisOp, int OtherOp>
252 SDTCisSubVecOfVec<0,1>, SDTCisInt<2>
255 SDTCisSubVecOfVec<2, 1>, SDTCisSameAs<0,1>, SDTCisInt<3>
656 SDTypeProfile<1, 2, [SDTCisSubVecOfVec<1, 0>, SDTCisSameAs<1, 2>]>,[]>;
/external/llvm/utils/TableGen/
DCodeGenDAGPatterns.h179 SDTCisSubVecOfVec, SDTCVecEltisVT, SDTCisSameNumEltsAs, SDTCisSameSizeAs enumerator
DCodeGenDAGPatterns.cpp934 ConstraintType = SDTCisSubVecOfVec; in SDTypeConstraint()
1060 case SDTCisSubVecOfVec: { in ApplyTypeConstraint()
/external/llvm-project/llvm/utils/TableGen/
DCodeGenDAGPatterns.h383 SDTCisSubVecOfVec, SDTCVecEltisVT, SDTCisSameNumEltsAs, SDTCisSameSizeAs enumerator
DCodeGenDAGPatterns.cpp1482 ConstraintType = SDTCisSubVecOfVec; in SDTypeConstraint()
1612 case SDTCisSubVecOfVec: { in ApplyTypeConstraint()
/external/llvm/lib/Target/X86/
DX86InstrFragmentsSIMD.td441 SDTCisSubVecOfVec<1, 0>]>, []>;
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/
DX86InstrFragmentsSIMD.td489 SDTCisSubVecOfVec<1, 0>]>, []>;
/external/llvm-project/llvm/lib/Target/X86/
DX86InstrFragmentsSIMD.td498 SDTCisSubVecOfVec<1, 0>]>, []>;
/external/llvm/lib/Target/Hexagon/
DHexagonInstrInfoV60.td1585 SDTCisSubVecOfVec<1, 0>]>;