Home
last modified time | relevance | path

Searched refs:SDWA (Results 1 – 25 of 56) sorted by relevance

123

/external/llvm-project/llvm/test/CodeGen/AMDGPU/
Dsdwa-preserve.mir1 …fiji -start-before=si-peephole-sdwa -verify-machineinstrs -o - %s | FileCheck -check-prefix=SDWA %s
2 …x900 -start-before=si-peephole-sdwa -verify-machineinstrs -o - %s | FileCheck -check-prefix=SDWA %s
4 # SDWA-LABEL: {{^}}add_f16_u32_preserve
6 # SDWA: flat_load_dword [[FIRST:v[0-9]+]], v[{{[0-9]+}}:{{[0-9]+}}]
7 # SDWA: flat_load_dword [[SECOND:v[0-9]+]], v[{{[0-9]+}}:{{[0-9]+}}]
9 # SDWA: v_mul_f32_sdwa [[RES:v[0-9]+]], [[FIRST]], [[SECOND]] dst_sel:WORD_1 dst_unused:UNUSED_PAD …
10 # SDWA: v_add_f16_sdwa [[RES:v[0-9]+]], [[FIRST]], [[SECOND]] dst_sel:BYTE_1 dst_unused:UNUSED_PRES…
12 # SDWA: flat_store_dword v[{{[0-9]+}}:{{[0-9]+}}], [[RES]]
59 # SDWA-LABEL: sdwa_preserve_keep
60 # SDWA: flat_load_dword [[FIRST:v[0-9]+]], v[{{[0-9]+}}:{{[0-9]+}}]
[all …]
Dbfe-combine.ll2 ; RUN: llc -march=amdgcn -mcpu=fiji < %s | FileCheck --check-prefix=GCN --check-prefix=VI-SDWA %s
8 ; VI-SDWA: v_mov_b32_e32 v[[SHIFT:[0-9]+]], 2
9 ; VI-SDWA: v_lshlrev_b32_sdwa v[[ADDRBASE:[0-9]+]], v[[SHIFT]], v{{[0-9]+}} dst_sel:DWORD dst_unuse…
13 ; VI-SDWA: v_add_u32_e32 v[[ADDRLO:[0-9]+]], vcc, s{{[0-9]+}}, v[[ADDRBASE]]
29 ; VI-SDWA: v_mov_b32_e32 v[[SHIFT:[0-9]+]], 15
30 ; VI-SDWA: v_lshlrev_b32_sdwa v[[ADDRBASE1:[0-9]+]], v[[SHIFT]], v{{[0-9]+}} dst_sel:DWORD dst_unus…
31 ; VI-SDWA: v_lshlrev_b64 v{{\[}}[[ADDRBASE:[0-9]+]]:{{[^\]+}}], 2, v{{\[}}[[ADDRBASE1]]:{{[^\]+}}]
32 ; VI-SDWA: v_add_u32_e32 v[[ADDRLO:[0-9]+]], vcc, s{{[0-9]+}}, v[[ADDRBASE]]
Dcttz_zero_undef.ll2 …strs < %s | FileCheck -enable-var-scope -check-prefix=SI -check-prefix=SI-SDWA -check-prefix=FUNC…
134 ; SI-SDWA: v_ffbl_b32_e32
147 ; SI-SDWA: v_ffbl_b32_e32
180 ; SI-SDWA: v_or_b32_e32
181 ; SI-SDWA: v_or_b32_sdwa
182 ; SI-SDWA: v_or_b32_e32
183 ; SI-SDWA: v_or_b32_sdwa
184 ; SI-SDWA: v_or_b32_e32 [[VAL1:v[0-9]+]], v{{[0-9]+}}, v{{[0-9]+}}
185 ; SI-SDWA: v_or_b32_e32 [[VAL2:v[0-9]+]], v{{[0-9]+}}, v{{[0-9]+}}
186 ; SI-SDWA: v_ffbl_b32_e32 v{{[0-9]+}}, [[VAL1]]
[all …]
Dimmv216.ll124 ; FIXME: Shouldn't need right shift and SDWA, also extra copy
149 ; FIXME: Shouldn't need right shift and SDWA, also extra copy
174 ; FIXME: Shouldn't need right shift and SDWA, also extra copy
195 ; FIXME: Shouldn't need right shift and SDWA, also extra copy
217 ; FIXME: Shouldn't need right shift and SDWA, also extra copy
238 ; FIXME: Shouldn't need right shift and SDWA, also extra copy
259 ; FIXME: Shouldn't need right shift and SDWA, also extra copy
280 ; FIXME: Shouldn't need right shift and SDWA, also extra copy
301 ; FIXME: Shouldn't need right shift and SDWA, also extra copy
365 ; FIXME: Shouldn't need right shift and SDWA, also extra copy
[all …]
Dsdwa-peephole.ll2 …phole -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=VI,GFX89,SDWA,GCN %s
3 …e -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GFX9,GFX9_10,SDWA,GCN %s
4 … -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GFX10,GFX9_10,SDWA,GCN %s
45 ; SDWA: v_mul_u32_u24_sdwa v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} dst_sel:DWORD dst_unused:UNUSED_PA…
62 ; SDWA-NOT: v_mul_u32_u24_sdwa
161 ; SDWA: v_mul_f16_e32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
162 ; SDWA-NOT: v_mul_f16_sdwa
257 ; SDWA-NOT: v_mul_u32_u24_sdwa
373 ; SDWA-DAG: v_cvt_f16_i16_e32 v{{[0-9]+}}, v{{[0-9]+}}
374 ; SDWA-DAG: v_cvt_f16_i16_sdwa v{{[0-9]+}}, v{{[0-9]+}} dst_sel:{{(WORD_1|DWORD)?}} dst_unused:UNUS…
[all …]
Dsdwa-stack.mir3 # Do not fold stack objects into SDWA.
Dlo16-lo16-physreg-copy-sgpr.mir4 # Note: GFX8 did not allow SDWA SGPR sources. Therefor no HI16 subregs can be used there.
Dlo16-hi16-illegal-copy.mir6 # Note: GFX8 did not allow SDWA SGPR sources. Therefor no HI16 subregs can be used there.
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/
DVOPInstructions.td381 def SDWA {
419 // GFX9 adds two features to SDWA:
420 // 1. Add 3 fields to the SDWA microcode word: S0, S1 and OMOD.
424 // 2. Add a new version of the SDWA microcode word for VOPC: SDWAB. This
430 // In GFX9, V_MAC_F16, V_MAC_F32 opcodes cannot be used with SDWA
432 // gfx9 SDWA basic encoding
452 // gfx9 SDWA-A
465 // gfx9 SDWA-B
492 let SDWA = 1;
497 let AsmVariantName = !if(P.HasExtSDWA, AMDGPUAsmVariants.SDWA,
[all …]
DSIPeepholeSDWA.cpp138 using namespace AMDGPU::SDWA;
393 DstUnused->getImm() == AMDGPU::SDWA::DstUnused::UNUSED_PRESERVE) { in convertToSDWA()
400 if (DstSel == AMDGPU::SDWA::SdwaSel::WORD_1 && in convertToSDWA()
401 getSrcSel() == AMDGPU::SDWA::SdwaSel::WORD_0) { in convertToSDWA()
465 getDstSel() != AMDGPU::SDWA::DWORD) { in convertToSDWA()
1090 SDWAInst.addImm(AMDGPU::SDWA::SdwaSel::DWORD); in convertToSDWA()
1100 SDWAInst.addImm(AMDGPU::SDWA::DstUnused::UNUSED_PAD); in convertToSDWA()
1110 SDWAInst.addImm(AMDGPU::SDWA::SdwaSel::DWORD); in convertToSDWA()
1120 SDWAInst.addImm(AMDGPU::SDWA::SdwaSel::DWORD); in convertToSDWA()
1127 DstUnused->getImm() == AMDGPU::SDWA::DstUnused::UNUSED_PRESERVE) { in convertToSDWA()
DSIDefines.h41 SDWA = 1 << 14, enumerator
230 SDWA = 2, enumerator
411 namespace SDWA {
DAMDGPU.td314 "Support SDWA (Sub-DWORD Addressing) extension"
320 "Support OMod with SDWA (Sub-DWORD Addressing) extension"
326 "Support scalar register with SDWA (Sub-DWORD Addressing) extension"
332 "Support scalar dst for VOPC with SDWA (Sub-DWORD Addressing) extension"
338 "Support v_mac_f32/f16 with SDWA (Sub-DWORD Addressing) extension"
344 "Support clamp for VOPC with SDWA (Sub-DWORD Addressing) extension"
917 string SDWA = "SDWA";
939 let Name = AMDGPUAsmVariants.SDWA;
DSIInstrFormats.td34 field bit SDWA = 0;
147 let TSFlags{14} = SDWA;
207 …let hasExtraSrcRegAllocReq = !if(VOP1,1,!if(VOP2,1,!if(VOP3,1,!if(VOPC,1,!if(SDWA,1, !if(VALU,1,0)…
DSIInstrInfo.td27 int SDWA = 2;
1455 // instructions with SDWA extension
1584 // Return type of input modifiers operand specified input operand for SDWA
1817 // Ins for SDWA
1861 // Outs for DPP and SDWA
1865 (outs), // no dst for VOPC, we use "vcc"-token as dst in SDWA VOPC instructions
1870 // Outs for SDWA
2050 // Function that checks if instruction supports DPP and SDWA
2054 0, // NumSrcArgs == 3 - No DPP or SDWA for VOP3
2056 0, // 64-bit dst - No DPP or SDWA for 64-bit operands
[all …]
/external/llvm-project/llvm/lib/Target/AMDGPU/
DVOPInstructions.td387 def SDWA {
425 // GFX9 adds two features to SDWA:
426 // 1. Add 3 fields to the SDWA microcode word: S0, S1 and OMOD.
430 // 2. Add a new version of the SDWA microcode word for VOPC: SDWAB. This
436 // In GFX9, V_MAC_F16, V_MAC_F32 opcodes cannot be used with SDWA
438 // gfx9 SDWA basic encoding
458 // gfx9 SDWA-A
471 // gfx9 SDWA-B
498 let SDWA = 1;
507 let AsmVariantName = !if(P.HasExtSDWA, AMDGPUAsmVariants.SDWA,
[all …]
DSIPeepholeSDWA.cpp138 using namespace AMDGPU::SDWA;
393 DstUnused->getImm() == AMDGPU::SDWA::DstUnused::UNUSED_PRESERVE) { in convertToSDWA()
400 if (DstSel == AMDGPU::SDWA::SdwaSel::WORD_1 && in convertToSDWA()
401 getSrcSel() == AMDGPU::SDWA::SdwaSel::WORD_0) { in convertToSDWA()
465 getDstSel() != AMDGPU::SDWA::DWORD) { in convertToSDWA()
1103 SDWAInst.addImm(AMDGPU::SDWA::SdwaSel::DWORD); in convertToSDWA()
1113 SDWAInst.addImm(AMDGPU::SDWA::DstUnused::UNUSED_PAD); in convertToSDWA()
1123 SDWAInst.addImm(AMDGPU::SDWA::SdwaSel::DWORD); in convertToSDWA()
1133 SDWAInst.addImm(AMDGPU::SDWA::SdwaSel::DWORD); in convertToSDWA()
1140 DstUnused->getImm() == AMDGPU::SDWA::DstUnused::UNUSED_PRESERVE) { in convertToSDWA()
DAMDGPU.td344 "Support SDWA (Sub-DWORD Addressing) extension"
350 "Support OMod with SDWA (Sub-DWORD Addressing) extension"
356 "Support scalar register with SDWA (Sub-DWORD Addressing) extension"
362 "Support scalar dst for VOPC with SDWA (Sub-DWORD Addressing) extension"
368 "Support v_mac_f32/f16 with SDWA (Sub-DWORD Addressing) extension"
374 "Support clamp for VOPC with SDWA (Sub-DWORD Addressing) extension"
1011 string SDWA = "SDWA";
1033 let Name = AMDGPUAsmVariants.SDWA;
DSIDefines.h41 SDWA = 1 << 14, enumerator
235 SDWA = 2, enumerator
606 namespace SDWA {
DSIInstrFormats.td34 field bit SDWA = 0;
155 let TSFlags{14} = SDWA;
213 let hasExtraSrcRegAllocReq = !or(VOP1, VOP2, VOP3, VOPC, SDWA, VALU);
DSIInstrInfo.td25 int SDWA = 2;
1445 // instructions with SDWA extension
1576 // Return type of input modifiers operand specified input operand for SDWA
1809 // Ins for SDWA
1857 (outs), // no dst for VOPC, we use "vcc"-token as dst in SDWA VOPC instructions
1862 // Outs for SDWA
2042 // Function that checks if instruction supports DPP and SDWA
2046 0, // NumSrcArgs == 3 - No DPP or SDWA for VOP3
2048 0, // 64-bit dst - No DPP or SDWA for 64-bit operands
2116 // HasSrc*FloatMods affects the SDWA encoding. We ignore EnableF32SrcMods.
[all …]
/external/llvm-project/llvm/docs/
DAMDGPUInstructionSyntax.rst126 they may also be encoded in *VOP3*, *DPP* and *SDWA* formats.
137 *SDWA* encoding _sdwa
DAMDGPUInstructionNotation.rst72 :ref:`SDWA operand modifiers<amdgpu_synid_sdwa_operand_modifiers>`.
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/MCTargetDesc/
DSIMCCodeEmitter.cpp366 using namespace AMDGPU::SDWA; in getSDWASrcEncoding()
396 using namespace AMDGPU::SDWA; in getSDWAVopcDstEncoding()
/external/llvm/lib/Target/AMDGPU/
DSIDefines.h32 SDWA = 1 << 14, enumerator
/external/llvm-project/llvm/lib/Target/AMDGPU/MCTargetDesc/
DSIMCCodeEmitter.cpp387 using namespace AMDGPU::SDWA; in getSDWASrcEncoding()
417 using namespace AMDGPU::SDWA; in getSDWAVopcDstEncoding()

123