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Searched refs:SDep (Results 1 – 25 of 85) sorted by relevance

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/external/llvm-project/llvm/lib/CodeGen/
DMacroFusion.cpp35 static bool isHazard(const SDep &Dep) { in isHazard()
36 return Dep.getKind() == SDep::Anti || Dep.getKind() == SDep::Output; in isHazard()
40 for (const SDep &SI : SU.Preds) in getPredClusterSU()
58 for (SDep &SI : FirstSU.Succs) in fuseInstructionPair()
62 for (SDep &SI : SecondSU.Preds) in fuseInstructionPair()
71 if (!DAG.addEdge(&SecondSU, SDep(&FirstSU, SDep::Cluster))) in fuseInstructionPair()
83 for (SDep &SI : FirstSU.Succs) in fuseInstructionPair()
87 for (SDep &SI : SecondSU.Preds) in fuseInstructionPair()
100 for (const SDep &SI : FirstSU.Succs) { in fuseInstructionPair()
107 DAG.addEdge(SU, SDep(&SecondSU, SDep::Artificial)); in fuseInstructionPair()
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DScheduleDAG.cpp75 LLVM_DUMP_METHOD void SDep::dump(const TargetRegisterInfo *TRI) const { in dump()
107 bool SUnit::addPred(const SDep &D, bool Required) { in addPred()
109 for (SDep &PredDep : Preds) { in addPred()
120 SDep ForwardD = PredDep; in addPred()
122 for (SDep &SuccDep : PredSU->Succs) { in addPred()
134 SDep P = D; in addPred()
138 if (D.getKind() == SDep::Data) { in addPred()
175 void SUnit::removePred(const SDep &D) { in removePred()
177 SmallVectorImpl<SDep>::iterator I = llvm::find(Preds, D); in removePred()
181 SDep P = D; in removePred()
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DScheduleDAGInstrs.cpp256 SDep Dep; in addPhysRegDataDeps()
258 Dep = SDep(SU, SDep::Artificial); in addPhysRegDataDeps()
263 Dep = SDep(SU, SDep::Data, *Alias); in addPhysRegDataDeps()
307 SDep::Kind Kind = MO.isUse() ? SDep::Anti : SDep::Output; in addPhysRegDeps()
316 (Kind != SDep::Output || !MO.isDead() || in addPhysRegDeps()
318 SDep Dep(SU, Kind, /*Reg=*/*Alias); in addPhysRegDeps()
319 if (Kind != SDep::Anti) in addPhysRegDeps()
446 SDep Dep(SU, SDep::Data, Reg); in addVRegDefDeps()
489 SDep Dep(SU, SDep::Output, Reg); in addVRegDefDeps()
537 V2SU.SU->addPred(SDep(SU, SDep::Anti, Reg)); in addVRegUseDeps()
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DMachinePipeliner.cpp693 if (SI.getKind() == SDep::Order) { in isSuccOrder()
785 SDep Dep(Load, SDep::Barrier); in addLoopCarriedDependences()
795 SDep Dep(Load, SDep::Barrier); in addLoopCarriedDependences()
803 SDep Dep(Load, SDep::Barrier); in addLoopCarriedDependences()
810 SDep Dep(Load, SDep::Barrier); in addLoopCarriedDependences()
820 SDep Dep(Load, SDep::Barrier); in addLoopCarriedDependences()
837 SmallVector<SDep, 4> RemoveDeps; in updatePhiDependences()
864 SDep Dep(SU, SDep::Anti, Reg); in updatePhiDependences()
872 I.addPred(SDep(SU, SDep::Barrier)); in updatePhiDependences()
884 SDep Dep(SU, SDep::Data, Reg); in updatePhiDependences()
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/external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/
DMacroFusion.cpp35 static bool isHazard(const SDep &Dep) { in isHazard()
36 return Dep.getKind() == SDep::Anti || Dep.getKind() == SDep::Output; in isHazard()
40 for (const SDep &SI : SU.Preds) in getPredClusterSU()
58 for (SDep &SI : FirstSU.Succs) in fuseInstructionPair()
62 for (SDep &SI : SecondSU.Preds) in fuseInstructionPair()
71 if (!DAG.addEdge(&SecondSU, SDep(&FirstSU, SDep::Cluster))) in fuseInstructionPair()
83 for (SDep &SI : FirstSU.Succs) in fuseInstructionPair()
87 for (SDep &SI : SecondSU.Preds) in fuseInstructionPair()
100 for (const SDep &SI : FirstSU.Succs) { in fuseInstructionPair()
107 DAG.addEdge(SU, SDep(&SecondSU, SDep::Artificial)); in fuseInstructionPair()
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DScheduleDAG.cpp75 LLVM_DUMP_METHOD void SDep::dump(const TargetRegisterInfo *TRI) const { in dump()
107 bool SUnit::addPred(const SDep &D, bool Required) { in addPred()
109 for (SDep &PredDep : Preds) { in addPred()
120 SDep ForwardD = PredDep; in addPred()
122 for (SDep &SuccDep : PredSU->Succs) { in addPred()
134 SDep P = D; in addPred()
138 if (D.getKind() == SDep::Data) { in addPred()
175 void SUnit::removePred(const SDep &D) { in removePred()
177 SmallVectorImpl<SDep>::iterator I = llvm::find(Preds, D); in removePred()
181 SDep P = D; in removePred()
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DScheduleDAGInstrs.cpp254 SDep Dep; in addPhysRegDataDeps()
256 Dep = SDep(SU, SDep::Artificial); in addPhysRegDataDeps()
261 Dep = SDep(SU, SDep::Data, *Alias); in addPhysRegDataDeps()
303 SDep::Kind Kind = MO.isUse() ? SDep::Anti : SDep::Output; in addPhysRegDeps()
312 (Kind != SDep::Output || !MO.isDead() || in addPhysRegDeps()
314 if (Kind == SDep::Anti) in addPhysRegDeps()
315 DefSU->addPred(SDep(SU, Kind, /*Reg=*/*Alias)); in addPhysRegDeps()
317 SDep Dep(SU, Kind, /*Reg=*/*Alias); in addPhysRegDeps()
444 SDep Dep(SU, SDep::Data, Reg); in addVRegDefDeps()
487 SDep Dep(SU, SDep::Output, Reg); in addVRegDefDeps()
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DMachinePipeliner.cpp613 if (SI.getKind() == SDep::Order) { in isSuccOrder()
702 SDep Dep(Load, SDep::Barrier); in addLoopCarriedDependences()
712 SDep Dep(Load, SDep::Barrier); in addLoopCarriedDependences()
720 SDep Dep(Load, SDep::Barrier); in addLoopCarriedDependences()
727 SDep Dep(Load, SDep::Barrier); in addLoopCarriedDependences()
739 SDep Dep(Load, SDep::Barrier); in addLoopCarriedDependences()
756 SmallVector<SDep, 4> RemoveDeps; in updatePhiDependences()
783 SDep Dep(SU, SDep::Anti, Reg); in updatePhiDependences()
791 I.addPred(SDep(SU, SDep::Barrier)); in updatePhiDependences()
803 SDep Dep(SU, SDep::Data, Reg); in updatePhiDependences()
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/external/llvm-project/llvm/lib/Target/AMDGPU/
DAMDGPUExportClustering.cpp69 for (const SDep &Pred : SUb->Preds) { in buildCluster()
72 DAG->addEdge(ChainHead, SDep(PredSU, SDep::Artificial)); in buildCluster()
76 DAG->addEdge(SUb, SDep(SUa, SDep::Barrier)); in buildCluster()
78 DAG->addEdge(SUb, SDep(SUa, SDep::Cluster)); in buildCluster()
83 SmallVector<SDep, 2> ToAdd, ToRemove; in removeExportDependencies()
85 for (const SDep &Pred : SU.Preds) { in removeExportDependencies()
94 for (const SDep &ExportPred : PredSU->Preds) { in removeExportDependencies()
97 ToAdd.push_back(SDep(ExportPredSU, SDep::Barrier)); in removeExportDependencies()
102 for (SDep Pred : ToRemove) in removeExportDependencies()
104 for (SDep Pred : ToAdd) in removeExportDependencies()
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/external/llvm-project/llvm/include/llvm/CodeGen/
DScheduleDAG.h49 class SDep {
101 SDep() : Dep(nullptr, Data) {} in SDep() function
104 SDep(SUnit *S, Kind kind, unsigned Reg) in SDep() function
123 SDep(SUnit *S, OrderKind kind) in SDep() function
129 bool overlaps(const SDep &Other) const;
131 bool operator==(const SDep &Other) const {
135 bool operator!=(const SDep &Other) const {
256 SmallVector<SDep, 4> Preds; ///< All sunit predecessors.
257 SmallVector<SDep, 4> Succs; ///< All sunit successors.
259 typedef SmallVectorImpl<SDep>::iterator pred_iterator;
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/external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/
DScheduleDAG.h49 class SDep {
101 SDep() : Dep(nullptr, Data) {} in SDep() function
104 SDep(SUnit *S, Kind kind, unsigned Reg) in SDep() function
123 SDep(SUnit *S, OrderKind kind) in SDep() function
129 bool overlaps(const SDep &Other) const;
131 bool operator==(const SDep &Other) const {
135 bool operator!=(const SDep &Other) const {
256 SmallVector<SDep, 4> Preds; ///< All sunit predecessors.
257 SmallVector<SDep, 4> Succs; ///< All sunit successors.
259 typedef SmallVectorImpl<SDep>::iterator pred_iterator;
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/external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/SelectionDAG/
DScheduleDAGFast.cpp88 void AddPred(SUnit *SU, const SDep &D) { in AddPred()
94 void RemovePred(SUnit *SU, const SDep &D) { in RemovePred()
99 void ReleasePred(SUnit *SU, SDep *PredEdge);
139 void ScheduleDAGFast::ReleasePred(SUnit *SU, SDep *PredEdge) { in ReleasePred()
162 for (SDep &Pred : SU->Preds) { in ReleasePredecessors()
192 for (SDep &Succ : SU->Succs) { in ScheduleNodeBottomUp()
277 SDep ChainPred; in CopyAndMoveSuccessors()
278 SmallVector<SDep, 4> ChainSuccs; in CopyAndMoveSuccessors()
279 SmallVector<SDep, 4> LoadPreds; in CopyAndMoveSuccessors()
280 SmallVector<SDep, 4> NodePreds; in CopyAndMoveSuccessors()
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DScheduleDAGRRList.cpp225 void AddPredQueued(SUnit *SU, const SDep &D) { in AddPredQueued()
233 void AddPred(SUnit *SU, const SDep &D) { in AddPred()
241 void RemovePred(SUnit *SU, const SDep &D) { in RemovePred()
252 void ReleasePred(SUnit *SU, const SDep *PredEdge);
259 void CapturePred(SDep *PredEdge);
398 void ScheduleDAGRRList::ReleasePred(SUnit *SU, const SDep *PredEdge) { in ReleasePred()
556 for (SDep &Pred : SU->Preds) { in ReleasePredecessors()
770 for (SDep &Succ : SU->Succs) { in ScheduleNodeBottomUp()
820 void ScheduleDAGRRList::CapturePred(SDep *PredEdge) { in CapturePred()
839 for (SDep &Pred : SU->Preds) { in UnscheduleNodeBottomUp()
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/external/llvm-project/llvm/lib/CodeGen/SelectionDAG/
DScheduleDAGFast.cpp88 void AddPred(SUnit *SU, const SDep &D) { in AddPred()
94 void RemovePred(SUnit *SU, const SDep &D) { in RemovePred()
99 void ReleasePred(SUnit *SU, SDep *PredEdge);
139 void ScheduleDAGFast::ReleasePred(SUnit *SU, SDep *PredEdge) { in ReleasePred()
162 for (SDep &Pred : SU->Preds) { in ReleasePredecessors()
192 for (SDep &Succ : SU->Succs) { in ScheduleNodeBottomUp()
277 SDep ChainPred; in CopyAndMoveSuccessors()
278 SmallVector<SDep, 4> ChainSuccs; in CopyAndMoveSuccessors()
279 SmallVector<SDep, 4> LoadPreds; in CopyAndMoveSuccessors()
280 SmallVector<SDep, 4> NodePreds; in CopyAndMoveSuccessors()
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DScheduleDAGRRList.cpp225 void AddPredQueued(SUnit *SU, const SDep &D) { in AddPredQueued()
233 void AddPred(SUnit *SU, const SDep &D) { in AddPred()
241 void RemovePred(SUnit *SU, const SDep &D) { in RemovePred()
252 void ReleasePred(SUnit *SU, const SDep *PredEdge);
259 void CapturePred(SDep *PredEdge);
398 void ScheduleDAGRRList::ReleasePred(SUnit *SU, const SDep *PredEdge) { in ReleasePred()
556 for (SDep &Pred : SU->Preds) { in ReleasePredecessors()
770 for (SDep &Succ : SU->Succs) { in ScheduleNodeBottomUp()
820 void ScheduleDAGRRList::CapturePred(SDep *PredEdge) { in CapturePred()
839 for (SDep &Pred : SU->Preds) { in UnscheduleNodeBottomUp()
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/external/llvm/include/llvm/CodeGen/
DScheduleDAG.h45 class SDep {
98 SDep() : Dep(nullptr, Data) {} in SDep() function
101 SDep(SUnit *S, Kind kind, unsigned Reg) in SDep() function
119 SDep(SUnit *S, OrderKind kind) in SDep() function
125 bool overlaps(const SDep &Other) const;
127 bool operator==(const SDep &Other) const {
131 bool operator!=(const SDep &Other) const {
241 struct isPodLike<SDep> { static const bool value = true; };
258 SmallVector<SDep, 4> Preds; // All sunit predecessors.
259 SmallVector<SDep, 4> Succs; // All sunit successors.
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/external/llvm/lib/CodeGen/SelectionDAG/
DScheduleDAGFast.cpp88 void AddPred(SUnit *SU, const SDep &D) { in AddPred()
94 void RemovePred(SUnit *SU, const SDep &D) { in RemovePred()
99 void ReleasePred(SUnit *SU, SDep *PredEdge);
140 void ScheduleDAGFast::ReleasePred(SUnit *SU, SDep *PredEdge) { in ReleasePred()
280 SDep ChainPred; in CopyAndMoveSuccessors()
281 SmallVector<SDep, 4> ChainSuccs; in CopyAndMoveSuccessors()
282 SmallVector<SDep, 4> LoadPreds; in CopyAndMoveSuccessors()
283 SmallVector<SDep, 4> NodePreds; in CopyAndMoveSuccessors()
284 SmallVector<SDep, 4> NodeSuccs; in CopyAndMoveSuccessors()
309 const SDep &Pred = LoadPreds[i]; in CopyAndMoveSuccessors()
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DScheduleDAGRRList.cpp199 void AddPred(SUnit *SU, const SDep &D) { in AddPred()
207 void RemovePred(SUnit *SU, const SDep &D) { in RemovePred()
218 void ReleasePred(SUnit *SU, const SDep *PredEdge);
225 void CapturePred(SDep *PredEdge);
365 void ScheduleDAGRRList::ReleasePred(SUnit *SU, const SDep *PredEdge) { in ReleasePred()
791 void ScheduleDAGRRList::CapturePred(SDep *PredEdge) { in CapturePred()
1025 SmallVector<SDep, 4> ChainPreds; in CopyAndMoveSuccessors()
1026 SmallVector<SDep, 4> ChainSuccs; in CopyAndMoveSuccessors()
1027 SmallVector<SDep, 4> LoadPreds; in CopyAndMoveSuccessors()
1028 SmallVector<SDep, 4> NodePreds; in CopyAndMoveSuccessors()
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/external/llvm/lib/CodeGen/
DScheduleDAG.cpp65 bool SUnit::addPred(const SDep &D, bool Required) { in addPred()
67 for (SmallVectorImpl<SDep>::iterator I = Preds.begin(), E = Preds.end(); in addPred()
78 SDep ForwardD = *I; in addPred()
80 for (SmallVectorImpl<SDep>::iterator II = PredSU->Succs.begin(), in addPred()
93 SDep P = D; in addPred()
97 if (D.getKind() == SDep::Data) { in addPred()
133 void SUnit::removePred(const SDep &D) { in removePred()
135 for (SmallVectorImpl<SDep>::iterator I = Preds.begin(), E = Preds.end(); in removePred()
139 SDep P = D; in removePred()
142 SmallVectorImpl<SDep>::iterator Succ = std::find(N->Succs.begin(), in removePred()
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DScheduleDAGInstrs.cpp303 SDep Dep; in addPhysRegDataDeps()
305 Dep = SDep(SU, SDep::Artificial); in addPhysRegDataDeps()
310 Dep = SDep(SU, SDep::Data, *Alias); in addPhysRegDataDeps()
336 SDep::Kind Kind = MO.isUse() ? SDep::Anti : SDep::Output; in addPhysRegDeps()
346 (Kind != SDep::Output || !MO.isDead() || in addPhysRegDeps()
348 if (Kind == SDep::Anti) in addPhysRegDeps()
349 DefSU->addPred(SDep(SU, Kind, /*Reg=*/*Alias)); in addPhysRegDeps()
351 SDep Dep(SU, Kind, /*Reg=*/*Alias); in addPhysRegDeps()
461 SDep Dep(SU, SDep::Data, Reg); in addVRegDefDeps()
504 SDep Dep(SU, SDep::Output, Reg); in addVRegDefDeps()
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/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/
DHexagonSubtarget.cpp132 SmallVector<SDep, 4> Erase; in apply()
134 if (D.getKind() == SDep::Output && D.getReg() == Hexagon::USR_OVF) in apply()
152 for (SDep &SI : SU.Succs) { in apply()
153 if (SI.getKind() != SDep::Order || SI.getLatency() != 0) in apply()
162 for (SDep &PI : SI.getSUnit()->Preds) { in apply()
163 if (PI.getSUnit() != &SU || PI.getKind() != SDep::Order) in apply()
211 DAG->addEdge(&DAG->SUnits[su], SDep(LastSequentialCall, SDep::Barrier)); in apply()
215 DAG->addEdge(&DAG->SUnits[su], SDep(&DAG->SUnits[su-1], SDep::Barrier)); in apply()
252 DAG->addEdge(&DAG->SUnits[su], SDep(LastVRegUse[*AI], SDep::Barrier)); in apply()
302 SDep A(&S0, SDep::Artificial); in apply()
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DHexagonVLIWPacketizer.cpp297 SDep::Kind DepType, unsigned DepReg) { in isCallDependent()
311 if (DepType == SDep::Data) { in isCallDependent()
320 static bool isRegDependence(const SDep::Kind DepType) { in isRegDependence()
321 return DepType == SDep::Data || DepType == SDep::Anti || in isRegDependence()
322 DepType == SDep::Output; in isRegDependence()
370 SDep::Kind DepType, MachineBasicBlock::iterator &MII, in promoteToDotCur()
372 assert(DepType == SDep::Data); in promoteToDotCur()
452 SDep::Kind DepType, MachineBasicBlock::iterator &MII, in promoteToDotNew()
454 assert(DepType == SDep::Data); in promoteToDotNew()
527 if (PI.getKind() != SDep::Anti && in updateOffset()
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/external/llvm-project/llvm/lib/Target/Hexagon/
DHexagonSubtarget.cpp202 SmallVector<SDep, 4> Erase; in apply()
204 if (D.getKind() == SDep::Output && D.getReg() == Hexagon::USR_OVF) in apply()
222 for (SDep &SI : SU.Succs) { in apply()
223 if (SI.getKind() != SDep::Order || SI.getLatency() != 0) in apply()
232 for (SDep &PI : SI.getSUnit()->Preds) { in apply()
233 if (PI.getSUnit() != &SU || PI.getKind() != SDep::Order) in apply()
281 DAG->addEdge(&DAG->SUnits[su], SDep(LastSequentialCall, SDep::Barrier)); in apply()
285 DAG->addEdge(&DAG->SUnits[su], SDep(&DAG->SUnits[su-1], SDep::Barrier)); in apply()
322 DAG->addEdge(&DAG->SUnits[su], SDep(LastVRegUse[*AI], SDep::Barrier)); in apply()
372 SDep A(&S0, SDep::Artificial); in apply()
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DHexagonVLIWPacketizer.cpp305 SDep::Kind DepType, unsigned DepReg) { in isCallDependent()
319 if (DepType == SDep::Data) { in isCallDependent()
328 static bool isRegDependence(const SDep::Kind DepType) { in isRegDependence()
329 return DepType == SDep::Data || DepType == SDep::Anti || in isRegDependence()
330 DepType == SDep::Output; in isRegDependence()
378 SDep::Kind DepType, MachineBasicBlock::iterator &MII, in promoteToDotCur()
380 assert(DepType == SDep::Data); in promoteToDotCur()
460 SDep::Kind DepType, MachineBasicBlock::iterator &MII, in promoteToDotNew()
462 assert(DepType == SDep::Data); in promoteToDotNew()
535 if (PI.getKind() != SDep::Anti && in updateOffset()
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/external/llvm/lib/Target/Hexagon/
DHexagonVLIWPacketizer.cpp269 SDep::Kind DepType, unsigned DepReg) { in isCallDependent()
284 if (HII->isIndirectCall(MI) && (DepType == SDep::Data)) { in isCallDependent()
293 static bool isRegDependence(const SDep::Kind DepType) { in isRegDependence()
294 return DepType == SDep::Data || DepType == SDep::Anti || in isRegDependence()
295 DepType == SDep::Output; in isRegDependence()
336 SDep::Kind DepType, MachineBasicBlock::iterator &MII, in promoteToDotCur()
338 assert(DepType == SDep::Data); in promoteToDotCur()
419 SDep::Kind DepType, MachineBasicBlock::iterator &MII, in promoteToDotNew()
421 assert (DepType == SDep::Data); in promoteToDotNew()
814 if (Dep.getSUnit() == PacketSUDep && Dep.getKind() == SDep::Anti && in restrictingDepExistInPacket()
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