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Searched refs:SECURE (Results 1 – 25 of 75) sorted by relevance

123

/external/arm-trusted-firmware/services/spd/tspd/
Dtspd_main.c64 assert(handle == cm_get_context(SECURE)); in tspd_handle_sp_preemption()
65 cm_el1_sysregs_context_save(SECURE); in tspd_handle_sp_preemption()
116 assert(&tsp_ctx->cpu_ctx == cm_get_context(SECURE)); in tspd_sel1_interrupt_handler()
139 cm_el1_sysregs_context_restore(SECURE); in tspd_sel1_interrupt_handler()
140 cm_set_elr_spsr_el3(SECURE, (uint64_t) &tsp_vectors->sel1_intr_entry, in tspd_sel1_interrupt_handler()
143 cm_set_next_eret_context(SECURE); in tspd_sel1_interrupt_handler()
167 assert(get_interrupt_src_ss(flags) == SECURE); in tspd_ns_interrupt_handler()
173 disable_intr_rm_local(INTR_TYPE_NS, SECURE); in tspd_ns_interrupt_handler()
196 tsp_ep_info = bl31_plat_get_next_image_ep_info(SECURE); in tspd_setup()
223 bl31_set_next_image_type(SECURE); in tspd_setup()
[all …]
Dtspd_common.c48 cm_set_context(&tsp_ctx->cpu_ctx, SECURE); in tspd_init_tsp_ep_state()
51 ep_attr = SECURE | EP_ST_ENABLE; in tspd_init_tsp_ep_state()
79 assert(cm_get_context(SECURE) == &tsp_ctx->cpu_ctx); in tspd_synchronous_sp_entry()
80 cm_el1_sysregs_context_restore(SECURE); in tspd_synchronous_sp_entry()
81 cm_set_next_eret_context(SECURE); in tspd_synchronous_sp_entry()
104 assert(cm_get_context(SECURE) == &tsp_ctx->cpu_ctx); in tspd_synchronous_sp_exit()
105 cm_el1_sysregs_context_save(SECURE); in tspd_synchronous_sp_exit()
131 cm_set_elr_el3(SECURE, in tspd_abort_preempted_smc()
Dtspd_pm.c46 cm_set_elr_el3(SECURE, (uint64_t) &tsp_vectors->cpu_off_entry); in tspd_cpu_off_handler()
85 cm_set_elr_el3(SECURE, (uint64_t) &tsp_vectors->cpu_suspend_entry); in tspd_cpu_suspend_handler()
128 disable_intr_rm_local(INTR_TYPE_NS, SECURE); in tspd_cpu_on_finish_handler()
163 cm_set_elr_el3(SECURE, (uint64_t) &tsp_vectors->cpu_resume_entry); in tspd_cpu_suspend_finish_handler()
205 cm_set_elr_el3(SECURE, (uint64_t) &tsp_vectors->system_off_entry); in tspd_system_off()
231 cm_set_elr_el3(SECURE, (uint64_t) &tsp_vectors->system_reset_entry); in tspd_system_reset()
/external/arm-trusted-firmware/services/spd/tlkd/
Dtlkd_common.c28 cm_el1_sysregs_context_save(SECURE); in tlkd_va_translate()
65 cm_el1_sysregs_context_restore(SECURE); in tlkd_va_translate()
68 write_scr(cm_get_scr_el3(SECURE)); in tlkd_va_translate()
95 cm_set_context(&tlk_ctx->cpu_ctx, SECURE); in tlkd_init_tlk_ep_state()
106 ep_attr = SECURE | EP_ST_ENABLE; in tlkd_init_tlk_ep_state()
131 assert(cm_get_context(SECURE) == &tlk_ctx->cpu_ctx); in tlkd_synchronous_sp_entry()
132 cm_el1_sysregs_context_restore(SECURE); in tlkd_synchronous_sp_entry()
133 cm_set_next_eret_context(SECURE); in tlkd_synchronous_sp_entry()
157 assert(cm_get_context(SECURE) == &tlk_ctx->cpu_ctx); in tlkd_synchronous_sp_exit()
158 cm_el1_sysregs_context_save(SECURE); in tlkd_synchronous_sp_exit()
Dtlkd_main.c72 disable_intr_rm_local(INTR_TYPE_S_EL1, SECURE); in tlkd_interrupt_handler()
82 s_cpu_context = cm_get_context(SECURE); in tlkd_interrupt_handler()
90 cm_el1_sysregs_context_restore(SECURE); in tlkd_interrupt_handler()
91 cm_set_next_eret_context(SECURE); in tlkd_interrupt_handler()
112 tlk_ep_info = bl31_plat_get_next_image_ep_info(SECURE); in tlkd_setup()
173 tlk_entry_point = bl31_plat_get_next_image_ep_info(SECURE); in tlkd_init()
233 assert(handle == cm_get_context(SECURE)); in tlkd_smc_handler()
234 cm_el1_sysregs_context_save(SECURE); in tlkd_smc_handler()
308 assert(&tlk_ctx.cpu_ctx == cm_get_context(SECURE)); in tlkd_smc_handler()
319 cm_el1_sysregs_context_restore(SECURE); in tlkd_smc_handler()
[all …]
/external/arm-trusted-firmware/services/spd/opteed/
Dopteed_main.c73 assert(&optee_ctx->cpu_ctx == cm_get_context(SECURE)); in opteed_sel1_interrupt_handler()
75 cm_set_elr_el3(SECURE, (uint64_t)&optee_vector_table->fiq_entry); in opteed_sel1_interrupt_handler()
76 cm_el1_sysregs_context_restore(SECURE); in opteed_sel1_interrupt_handler()
77 cm_set_next_eret_context(SECURE); in opteed_sel1_interrupt_handler()
109 optee_ep_info = bl31_plat_get_next_image_ep_info(SECURE); in opteed_setup()
167 optee_entry_point = bl31_plat_get_next_image_ep_info(SECURE); in opteed_init()
232 assert(&optee_ctx->cpu_ctx == cm_get_context(SECURE)); in opteed_smc_handler()
239 cm_set_elr_el3(SECURE, (uint64_t) in opteed_smc_handler()
242 cm_set_elr_el3(SECURE, (uint64_t) in opteed_smc_handler()
246 cm_el1_sysregs_context_restore(SECURE); in opteed_smc_handler()
[all …]
Dopteed_common.c39 cm_set_context(&optee_ctx->cpu_ctx, SECURE); in opteed_init_optee_ep_state()
42 ep_attr = SECURE | EP_ST_ENABLE; in opteed_init_optee_ep_state()
78 assert(cm_get_context(SECURE) == &optee_ctx->cpu_ctx); in opteed_synchronous_sp_entry()
79 cm_el1_sysregs_context_restore(SECURE); in opteed_synchronous_sp_entry()
80 cm_set_next_eret_context(SECURE); in opteed_synchronous_sp_entry()
103 assert(cm_get_context(SECURE) == &optee_ctx->cpu_ctx); in opteed_synchronous_sp_exit()
104 cm_el1_sysregs_context_save(SECURE); in opteed_synchronous_sp_exit()
Dopteed_pm.c39 cm_set_elr_el3(SECURE, (uint64_t) &optee_vector_table->cpu_off_entry); in opteed_cpu_off_handler()
75 cm_set_elr_el3(SECURE, (uint64_t) &optee_vector_table->cpu_suspend_entry); in opteed_cpu_suspend_handler()
144 cm_set_elr_el3(SECURE, (uint64_t) &optee_vector_table->cpu_resume_entry); in opteed_cpu_suspend_finish_handler()
180 cm_set_elr_el3(SECURE, (uint64_t) &optee_vector_table->system_off_entry); in opteed_system_off()
200 cm_set_elr_el3(SECURE, (uint64_t) &optee_vector_table->system_reset_entry); in opteed_system_reset()
/external/llvm-project/llvm/test/CodeGen/PowerPC/
Dppc32-secure-plt-tls2.ll1 …triple=powerpc -mattr=+secure-plt -relocation-model=pic | FileCheck -check-prefix=SECURE-PLT-TLS %s
14 ; SECURE-PLT-TLS: mflr 30
15 ; SECURE-PLT-TLS-NEXT: addis 30, 30, _GLOBAL_OFFSET_TABLE_-.L0$pb@ha
16 ; SECURE-PLT-TLS-NEXT: addi 30, 30, _GLOBAL_OFFSET_TABLE_-.L0$pb@l
17 ; SECURE-PLT-TLS: addi 3, 30, a@got@tlsgd
18 ; SECURE-PLT-TLS: bl __tls_get_addr(a@tlsgd)@PLT{{$}}
Dppc32-secure-plt-tls.ll1 …nown-linux-gnu -mattr=+secure-plt -relocation-model=pic | FileCheck -check-prefix=SECURE-PLT-TLS %s
14 ; SECURE-PLT-TLS: mflr 30
15 ; SECURE-PLT-TLS-NEXT: addis 30, 30, .LTOC-.L0$pb@ha
16 ; SECURE-PLT-TLS-NEXT: addi 30, 30, .LTOC-.L0$pb@l
17 ; SECURE-PLT-TLS-NEXT: bl .L{{.*}}
18 ; SECURE-PLT-TLS: bl __tls_get_addr(a@tlsgd)@PLT+32768
Dppc32-pic.ll22 ; SMALL-SECURE: bl .L0$pb
24 ; SMALL-SECURE: addis 30, 30, _GLOBAL_OFFSET_TABLE_-.Lo$pb@ha
25 ; SMALL-SECURE: addi 30, 30, _GLOBAL_OFFSET_TABLE_-.Lo$pb@l
/external/arm-trusted-firmware/plat/arm/common/aarch64/
Darm_bl2_mem_params_desc.c27 VERSION_2, entry_point_info_t, SECURE | NON_EXECUTABLE),
45 SECURE | EXECUTABLE | EP_FIRST_EXE),
65 SECURE | EXECUTABLE | EP_FIRST_EXE),
97 VERSION_2, entry_point_info_t, SECURE | NON_EXECUTABLE),
108 VERSION_2, entry_point_info_t, SECURE | EXECUTABLE),
127 VERSION_2, entry_point_info_t, SECURE | NON_EXECUTABLE),
145 VERSION_2, entry_point_info_t, SECURE | NON_EXECUTABLE),
160 VERSION_2, entry_point_info_t, SECURE | NON_EXECUTABLE),
/external/arm-trusted-firmware/plat/qemu/common/
Dqemu_bl2_mem_params_desc.c27 SECURE | EXECUTABLE | EP_FIRST_EXE),
44 SECURE | EXECUTABLE | EP_FIRST_EXE),
66 #define BL32_EP_ATTRIBS (SECURE | EXECUTABLE)
69 #define BL32_EP_ATTRIBS (SECURE | EXECUTABLE | EP_FIRST_EXE)
97 entry_point_info_t, SECURE | NON_EXECUTABLE),
115 entry_point_info_t, SECURE | NON_EXECUTABLE),
/external/arm-trusted-firmware/plat/hisilicon/poplar/
Dbl2_plat_mem_params_desc.c28 VERSION_2, entry_point_info_t, SECURE | NON_EXECUTABLE),
46 SECURE | EXECUTABLE | EP_FIRST_EXE),
66 SECURE | EXECUTABLE | EP_FIRST_EXE),
92 VERSION_2, entry_point_info_t, SECURE | EXECUTABLE),
111 VERSION_2, entry_point_info_t, SECURE | NON_EXECUTABLE),
129 VERSION_2, entry_point_info_t, SECURE | NON_EXECUTABLE),
/external/arm-trusted-firmware/plat/hisilicon/hikey960/
Dhikey960_bl2_mem_params_desc.c28 VERSION_2, entry_point_info_t, SECURE | NON_EXECUTABLE),
46 SECURE | EXECUTABLE | EP_FIRST_EXE),
66 SECURE | EXECUTABLE | EP_FIRST_EXE),
92 VERSION_2, entry_point_info_t, SECURE | EXECUTABLE),
111 VERSION_2, entry_point_info_t, SECURE | NON_EXECUTABLE),
129 VERSION_2, entry_point_info_t, SECURE | NON_EXECUTABLE),
/external/arm-trusted-firmware/plat/hisilicon/hikey/
Dhikey_bl2_mem_params_desc.c28 VERSION_2, entry_point_info_t, SECURE | NON_EXECUTABLE),
46 SECURE | EXECUTABLE | EP_FIRST_EXE),
66 SECURE | EXECUTABLE | EP_FIRST_EXE),
92 VERSION_2, entry_point_info_t, SECURE | EXECUTABLE),
111 VERSION_2, entry_point_info_t, SECURE | NON_EXECUTABLE),
129 VERSION_2, entry_point_info_t, SECURE | NON_EXECUTABLE),
/external/arm-trusted-firmware/plat/marvell/armada/common/aarch64/
Dmarvell_bl2_mem_params_desc.c29 VERSION_2, entry_point_info_t, SECURE | NON_EXECUTABLE),
47 SECURE | EXECUTABLE | EP_FIRST_EXE),
67 SECURE | EXECUTABLE | EP_FIRST_EXE),
93 VERSION_2, entry_point_info_t, SECURE | EXECUTABLE),
113 VERSION_2, entry_point_info_t, SECURE | NON_EXECUTABLE),
132 VERSION_2, entry_point_info_t, SECURE | NON_EXECUTABLE),
/external/arm-trusted-firmware/bl1/
Dbl1_fwu.c245 if (GET_SECURITY_STATE(flags) == SECURE) { in bl1_fwu_image_copy()
382 if (GET_SECURITY_STATE(flags) == SECURE) { in bl1_fwu_image_auth()
389 if (GET_SECURITY_STATE(desc->ep_info.h.attr) == SECURE) { in bl1_fwu_image_auth()
519 (GET_SECURITY_STATE(flags) == SECURE) || in bl1_fwu_image_execute()
541 *handle = cm_get_context(SECURE); in bl1_fwu_image_execute()
543 *handle = smc_get_ctx(SECURE); in bl1_fwu_image_execute()
573 assert(GET_SECURITY_STATE(desc->ep_info.h.attr) == SECURE); in bl1_fwu_image_resume()
576 if (caller_sec_state == SECURE) { in bl1_fwu_image_resume()
587 resume_sec_state = SECURE; in bl1_fwu_image_resume()
591 (resume_sec_state == SECURE) ? "secure" : "normal"); in bl1_fwu_image_resume()
[all …]
/external/arm-trusted-firmware/services/std_svc/spmd/
Dspmd_main.c108 cm_set_context(&(spmc_ctx->cpu_ctx), SECURE); in spmd_spm_core_sync_entry()
111 cm_el1_sysregs_context_restore(SECURE); in spmd_spm_core_sync_entry()
114 cm_el2_sysregs_context_restore(SECURE); in spmd_spm_core_sync_entry()
116 cm_set_next_eret_context(SECURE); in spmd_spm_core_sync_entry()
122 cm_el1_sysregs_context_save(SECURE); in spmd_spm_core_sync_entry()
124 cm_el2_sysregs_context_save(SECURE); in spmd_spm_core_sync_entry()
139 assert(cm_get_context(SECURE) == &(ctx->cpu_ctx)); in spmd_spm_core_sync_exit()
254 ep_attr = SECURE | EP_ST_ENABLE; in spmd_spmc_init()
308 spmc_ep_info = bl31_plat_get_next_image_ep_info(SECURE); in spmd_setup()
347 unsigned int secure_state_in = (secure_origin) ? SECURE : NON_SECURE; in spmd_smc_forward()
[all …]
/external/arm-trusted-firmware/services/std_svc/spm_mm/
Dspm_mm_main.c95 cm_set_context(&(ctx->cpu_ctx), SECURE); in spm_sp_synchronous_entry()
98 cm_el1_sysregs_context_restore(SECURE); in spm_sp_synchronous_entry()
99 cm_set_next_eret_context(SECURE); in spm_sp_synchronous_entry()
109 cm_el1_sysregs_context_save(SECURE); in spm_sp_synchronous_entry()
290 assert(handle == cm_get_context(SECURE)); in spm_mm_smc_handler()
293 cm_set_elr_spsr_el3(SECURE, read_elr_el1(), read_spsr_el1()); in spm_mm_smc_handler()
/external/arm-trusted-firmware/plat/rpi/rpi3/aarch64/
Drpi3_bl2_mem_params_desc.c29 SECURE | EXECUTABLE | EP_FIRST_EXE),
56 SECURE | EXECUTABLE),
77 SECURE | NON_EXECUTABLE),
98 SECURE | NON_EXECUTABLE),
/external/arm-trusted-firmware/services/spd/trusty/
Dtrusty.c239 entry_point_info_t *ep_info = bl31_plat_get_next_image_ep_info(SECURE); in trusty_smc_handler()
256 ret = trusty_context_switch(SECURE, x1, 0, 0, 0); in trusty_smc_handler()
318 ep_info = bl31_plat_get_next_image_ep_info(SECURE); in trusty_init()
324 cm_set_context(&ctx->cpu_ctx, SECURE); in trusty_init()
334 cm_set_elr_el3(SECURE, ep_info->pc + (1U << 5)); in trusty_init()
337 cm_el1_sysregs_context_restore(SECURE); in trusty_init()
338 fpregs_context_restore(get_fpregs_ctx(cm_get_context(SECURE))); in trusty_init()
339 cm_set_next_eret_context(SECURE); in trusty_init()
433 ep_info = bl31_plat_get_next_image_ep_info(SECURE); in trusty_setup()
462 SET_PARAM_HEAD(ep_info, PARAM_EP, VERSION_1, SECURE | EP_ST_ENABLE); in trusty_setup()
/external/arm-trusted-firmware/bl1/tbbr/
Dtbbr_img_desc.c20 VERSION_1, entry_point_info_t, SECURE),
38 VERSION_1, entry_point_info_t, SECURE),
49 VERSION_1, entry_point_info_t, SECURE | EXECUTABLE),
/external/arm-trusted-firmware/plat/imx/imx7/common/
Dimx7_bl2_mem_params_desc.c19 SECURE | EXECUTABLE | EP_FIRST_EXE),
35 SECURE | NON_EXECUTABLE),
50 SECURE | NON_EXECUTABLE),
/external/arm-trusted-firmware/plat/intel/soc/common/
Dbl2_plat_mem_params_desc.c28 VERSION_2, entry_point_info_t, SECURE | NON_EXECUTABLE),
46 SECURE | EXECUTABLE | EP_FIRST_EXE),
66 SECURE | EXECUTABLE | EP_FIRST_EXE),

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