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Searched refs:SETEQ (Results 1 – 25 of 152) sorted by relevance

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/external/llvm/lib/Target/WebAssembly/
DWebAssemblyInstrInteger.td43 defm EQ : ComparisonInt<SETEQ, "eq ">;
60 [(set I32:$dst, (setcc I32:$src, 0, SETEQ))],
63 [(set I32:$dst, (setcc I64:$src, 0, SETEQ))],
/external/llvm/lib/Target/Hexagon/
DHexagonSelectCCInfo.td15 IntRegs:$fval, SETEQ)),
77 // Convert Rd = selectcc(p0, p1, true_val, false_val, SETEQ) into:
88 IntRegs:$fval, SETEQ)),
/external/llvm/lib/CodeGen/SelectionDAG/
DTargetLowering.cpp161 case ISD::SETEQ: in softenSetCCOperands()
1293 (Cond != ISD::SETEQ && Cond != ISD::SETNE)) in simplifySetCCWithAnd()
1382 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) && in SimplifySetCC()
1384 if ((C1 == 0) == (Cond == ISD::SETEQ)) { in SimplifySetCC()
1391 Cond = ISD::SETEQ; in SimplifySetCC()
1416 ISD::CondCode CC = Cond == ISD::SETULT ? ISD::SETEQ : ISD::SETNE; in SimplifySetCC()
1425 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) && in SimplifySetCC()
1492 bool Inverse = (N1C->isNullValue() && Cond == ISD::SETEQ) || in SimplifySetCC()
1579 case ISD::SETEQ: return DAG.getConstant(0, dl, VT); in SimplifySetCC()
1598 case ISD::SETEQ: in SimplifySetCC()
[all …]
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/WebAssembly/
DWebAssemblyInstrInteger.td73 defm EQ : ComparisonInt<SETEQ, "eq ", 0x46, 0x51>;
90 [(set I32:$dst, (setcc I32:$src, 0, SETEQ))],
93 [(set I32:$dst, (setcc I64:$src, 0, SETEQ))],
/external/llvm-project/llvm/lib/Target/WebAssembly/
DWebAssemblyInstrInteger.td73 defm EQ : ComparisonInt<SETEQ, "eq ", 0x46, 0x51>;
90 [(set I32:$dst, (setcc I32:$src, 0, SETEQ))],
93 [(set I32:$dst, (setcc I64:$src, 0, SETEQ))],
/external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/SelectionDAG/
DTargetLowering.cpp311 case ISD::SETEQ: in softenSetCCOperands()
2856 (Cond != ISD::SETEQ && Cond != ISD::SETNE)) in foldSetCCWithAnd()
2940 NewCond = ISD::CondCode::SETEQ; in optimizeSetCCOfSignedTruncationCheck()
2942 NewCond = ISD::CondCode::SETEQ; in optimizeSetCCOfSignedTruncationCheck()
3009 assert((Cond == ISD::SETEQ || Cond == ISD::SETNE) && in optimizeSetCCByHoistingAndByConstFromLogicalShift()
3082 assert((Cond == ISD::SETEQ || Cond == ISD::SETNE) && "Unexpected condcode"); in foldSetCCWithBinOp()
3159 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) && in SimplifySetCC()
3161 if ((C1 == 0) == (Cond == ISD::SETEQ)) { in SimplifySetCC()
3168 Cond = ISD::SETEQ; in SimplifySetCC()
3193 ISD::CondCode CC = Cond == ISD::SETULT ? ISD::SETEQ : ISD::SETNE; in SimplifySetCC()
[all …]
/external/llvm-project/llvm/lib/CodeGen/SelectionDAG/
DTargetLowering.cpp303 case ISD::SETEQ: in softenSetCCOperands()
3122 (Cond != ISD::SETEQ && Cond != ISD::SETNE)) in foldSetCCWithAnd()
3206 NewCond = ISD::CondCode::SETEQ; in optimizeSetCCOfSignedTruncationCheck()
3208 NewCond = ISD::CondCode::SETEQ; in optimizeSetCCOfSignedTruncationCheck()
3275 assert((Cond == ISD::SETEQ || Cond == ISD::SETNE) && in optimizeSetCCByHoistingAndByConstFromLogicalShift()
3348 assert((Cond == ISD::SETEQ || Cond == ISD::SETNE) && "Unexpected condcode"); in foldSetCCWithBinOp()
3421 ISD::CondCode CC = Cond == ISD::SETULT ? ISD::SETEQ : ISD::SETNE; in simplifySetCCWithCTPOP()
3426 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) && C1 == 1) { in simplifySetCCWithCTPOP()
3443 unsigned LogicOpcode = Cond == ISD::SETEQ ? ISD::AND : ISD::OR; in simplifySetCCWithCTPOP()
3502 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) && in SimplifySetCC()
[all …]
/external/llvm-project/llvm/test/TableGen/
DGlobalISelEmitter-setcc.td19 [(set GPR32:$dst, (i32 (setcc i32:$src0, i32:$src1, SETEQ)))]>;
/external/llvm-project/llvm/lib/Target/VE/
DVEISelDAGToDAG.cpp31 case ISD::SETEQ: in intCondCode2Icc()
61 case ISD::SETEQ: in fpCondCode2Fcc()
/external/llvm/lib/CodeGen/
DTargetLoweringBase.cpp763 CCs[RTLIB::OEQ_F32] = ISD::SETEQ; in InitCmpLibcallCCs()
764 CCs[RTLIB::OEQ_F64] = ISD::SETEQ; in InitCmpLibcallCCs()
765 CCs[RTLIB::OEQ_F128] = ISD::SETEQ; in InitCmpLibcallCCs()
766 CCs[RTLIB::OEQ_PPCF128] = ISD::SETEQ; in InitCmpLibcallCCs()
791 CCs[RTLIB::O_F32] = ISD::SETEQ; in InitCmpLibcallCCs()
792 CCs[RTLIB::O_F64] = ISD::SETEQ; in InitCmpLibcallCCs()
793 CCs[RTLIB::O_F128] = ISD::SETEQ; in InitCmpLibcallCCs()
794 CCs[RTLIB::O_PPCF128] = ISD::SETEQ; in InitCmpLibcallCCs()
DAnalysis.cpp186 case ISD::SETOEQ: case ISD::SETUEQ: return ISD::SETEQ; in getFCmpCodeWithoutNaN()
201 case ICmpInst::ICMP_EQ: return ISD::SETEQ; in getICmpCondCode()
/external/llvm/include/llvm/CodeGen/
DISDOpcodes.h870 SETEQ, // 1 X 0 0 1 True if equal enumerator
/external/llvm/lib/Target/AMDGPU/
DAMDGPUISelLowering.cpp970 case ISD::SETEQ: in CombineFMinMaxLegacy()
1374 SDValue REM_Lo = DAG.getSelectCC(DL, RHS_Hi, zero, REM_Part, LHS_Hi, ISD::SETEQ); in LowerUDIVREM64()
1378 SDValue DIV_Hi = DAG.getSelectCC(DL, RHS_Hi, zero, DIV_Part, zero, ISD::SETEQ); in LowerUDIVREM64()
1448 ISD::SETEQ); in LowerUDIVREM()
1462 ISD::SETEQ); in LowerUDIVREM()
1499 Quotient, Quotient_A_One, ISD::SETEQ); in LowerUDIVREM()
1503 Quotient_S_One, Div, ISD::SETEQ); in LowerUDIVREM()
1515 Remainder, Remainder_S_Den, ISD::SETEQ); in LowerUDIVREM()
1519 Remainder_A_Den, Rem, ISD::SETEQ); in LowerUDIVREM()
1797 SDValue ExpEqNegOne = DAG.getSetCC(SL, SetCCVT, NegOne, Exp, ISD::SETEQ); in LowerFROUND64()
[all …]
/external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/
DISDOpcodes.h1067 SETEQ, // 1 X 0 0 1 True if equal enumerator
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/
DAMDGPUISelLowering.cpp1272 case ISD::SETEQ: in combineFMinMaxLegacy()
1754 SDValue C3 = DAG.getSelectCC(DL, Sub1_Hi, RHS_Hi, C2, C1, ISD::SETEQ); in LowerUDIVREM64()
1776 SDValue C6 = DAG.getSelectCC(DL, Sub2_Hi, RHS_Hi, C5, C4, ISD::SETEQ); in LowerUDIVREM64()
1810 SDValue REM_Lo = DAG.getSelectCC(DL, RHS_Hi, Zero, REM_Part, LHS_Hi, ISD::SETEQ); in LowerUDIVREM64()
1814 SDValue DIV_Hi = DAG.getSelectCC(DL, RHS_Hi, Zero, DIV_Part, Zero, ISD::SETEQ); in LowerUDIVREM64()
1884 ISD::SETEQ); in LowerUDIVREM()
1898 ISD::SETEQ); in LowerUDIVREM()
1935 Quotient, Quotient_A_One, ISD::SETEQ); in LowerUDIVREM()
1939 Quotient_S_One, Div, ISD::SETEQ); in LowerUDIVREM()
1951 Remainder, Remainder_S_Den, ISD::SETEQ); in LowerUDIVREM()
[all …]
/external/llvm-project/llvm/include/llvm/CodeGen/
DISDOpcodes.h1283 SETEQ, // 1 X 0 0 1 True if equal enumerator
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/PowerPC/
DPPCISelDAGToDAG.cpp2917 case ISD::SETEQ: { in get32BitZExtCompare()
3091 case ISD::SETEQ: { in get32BitSExtCompare()
3262 case ISD::SETEQ: { in get64BitZExtCompare()
3419 case ISD::SETEQ: { in get64BitSExtCompare()
3702 if (CC == ISD::SETEQ || CC == ISD::SETNE) { in SelectCC()
3746 if (CC == ISD::SETEQ || CC == ISD::SETNE) { in SelectCC()
3794 case ISD::SETEQ: in SelectCC()
3821 case ISD::SETEQ: in SelectCC()
3865 case ISD::SETEQ: in getPredicateForSetCC()
3902 case ISD::SETEQ: return 2; // Bit #2 = SETOEQ in getCRIdxForSetCC()
[all …]
DPPCInstrInfo.td3408 def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETEQ)),
3506 defm : ExtSetCCPat<SETEQ,
3616 defm : ExtSetCCShiftPat<SETEQ,
3635 def : Pat<(i1 (setcc i32:$s1, imm32SExt16:$imm, SETEQ)),
3637 def : Pat<(i1 (setcc i32:$s1, immZExt16:$imm, SETEQ)),
3651 def : Pat<(i1 (setcc i32:$s1, imm:$imm, SETEQ)),
3663 def : Pat<(i1 (setcc i32:$s1, i32:$s2, SETEQ)),
3675 def : Pat<(i1 (setcc i64:$s1, imm64SExt16:$imm, SETEQ)),
3677 def : Pat<(i1 (setcc i64:$s1, immZExt16:$imm, SETEQ)),
3691 def : Pat<(i1 (setcc i64:$s1, imm64ZExt32:$imm, SETEQ)),
[all …]
/external/llvm-project/llvm/lib/Target/PowerPC/
DPPCISelDAGToDAG.cpp2877 case ISD::SETEQ: { in get32BitZExtCompare()
3051 case ISD::SETEQ: { in get32BitSExtCompare()
3222 case ISD::SETEQ: { in get64BitZExtCompare()
3379 case ISD::SETEQ: { in get64BitSExtCompare()
3668 if (CC == ISD::SETEQ || CC == ISD::SETNE) { in SelectCC()
3712 if (CC == ISD::SETEQ || CC == ISD::SETNE) { in SelectCC()
3760 case ISD::SETEQ: in SelectCC()
3787 case ISD::SETEQ: in SelectCC()
3836 case ISD::SETEQ: in getPredicateForSetCC()
3873 case ISD::SETEQ: return 2; // Bit #2 = SETOEQ in getCRIdxForSetCC()
[all …]
/external/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/Mips/
DMipsGenDAGISel.inc1401 /* 2516*/ OPC_CheckChild2CondCode, ISD::SETEQ,
1412 …i64] }, (imm:{ *:[i64] })<<P:Predicate_immZExt5_64>>:$p)), 0:{ *:[i64] }, SETEQ:{ *:[Other] }), (b…
1443 /* 2589*/ OPC_CheckChild2CondCode, ISD::SETEQ,
1454 …i64] }, (imm:{ *:[i64] })<<P:Predicate_immZExt5_64>>:$p)), 0:{ *:[i64] }, SETEQ:{ *:[Other] }), (b…
1490 /* 2667*/ OPC_CheckChild2CondCode, ISD::SETEQ,
1501 …P:Predicate_immZExt5_64>>:$p), GPR64Opnd:{ *:[i64] }:$rs), 0:{ *:[i64] }, SETEQ:{ *:[Other] }), (b…
1533 /* 2741*/ OPC_CheckChild2CondCode, ISD::SETEQ,
1544 …P:Predicate_immZExt5_64>>:$p), GPR64Opnd:{ *:[i64] }:$rs), 0:{ *:[i64] }, SETEQ:{ *:[Other] }), (b…
1573 /* 2806*/ OPC_CheckChild2CondCode, ISD::SETEQ,
1586 …:$lhs, (imm:{ *:[i64] })<<P:Predicate_PowerOf2LO>>:$mask), 0:{ *:[i64] }, SETEQ:{ *:[Other] }), (b…
[all …]
/external/llvm/lib/Target/PowerPC/
DPPCISelDAGToDAG.cpp1992 if (CC == ISD::SETEQ || CC == ISD::SETNE) { in SelectCC()
2036 if (CC == ISD::SETEQ || CC == ISD::SETNE) { in SelectCC()
2098 case ISD::SETEQ: return PPC::PRED_EQ; in getPredicateForSetCC()
2129 case ISD::SETEQ: return 2; // Bit #2 = SETOEQ in getCRIdxForSetCC()
2170 case ISD::SETNE: CC = ISD::SETEQ; Negate = true; break; in getVCmpInst()
2178 case ISD::SETEQ: in getVCmpInst()
2214 case ISD::SETNE: CC = ISD::SETEQ; Negate = true; break; in getVCmpInst()
2222 case ISD::SETEQ: in getVCmpInst()
2277 case ISD::SETEQ: { in trySETCC()
2312 case ISD::SETEQ: in trySETCC()
[all …]
/external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/
DAnalysis.cpp225 case ISD::SETOEQ: case ISD::SETUEQ: return ISD::SETEQ; in getFCmpCodeWithoutNaN()
240 case ICmpInst::ICMP_EQ: return ISD::SETEQ; in getICmpCondCode()
DTargetLoweringBase.cpp538 CCs[RTLIB::OEQ_F32] = ISD::SETEQ; in InitCmpLibcallCCs()
539 CCs[RTLIB::OEQ_F64] = ISD::SETEQ; in InitCmpLibcallCCs()
540 CCs[RTLIB::OEQ_F128] = ISD::SETEQ; in InitCmpLibcallCCs()
541 CCs[RTLIB::OEQ_PPCF128] = ISD::SETEQ; in InitCmpLibcallCCs()
/external/llvm-project/llvm/lib/CodeGen/
DAnalysis.cpp226 case ISD::SETOEQ: case ISD::SETUEQ: return ISD::SETEQ; in getFCmpCodeWithoutNaN()
241 case ICmpInst::ICMP_EQ: return ISD::SETEQ; in getICmpCondCode()
/external/llvm-project/llvm/lib/Target/AMDGPU/
DSIInsertSkips.cpp279 case ISD::SETEQ: in kill()

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