| /external/llvm/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 854 SETOGT, // 0 0 1 0 True if ordered and greater than enumerator
|
| /external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 1051 SETOGT, // 0 0 1 0 True if ordered and greater than enumerator
|
| /external/llvm-project/llvm/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 1267 SETOGT, // 0 0 1 0 True if ordered and greater than enumerator
|
| /external/llvm/lib/CodeGen/ |
| D | Analysis.cpp | 166 case FCmpInst::FCMP_OGT: return ISD::SETOGT; in getFCmpCondCode()
190 case ISD::SETOGT: case ISD::SETUGT: return ISD::SETGT; in getFCmpCodeWithoutNaN()
|
| /external/llvm/lib/Target/WebAssembly/ |
| D | WebAssemblyInstrFloat.td | 59 defm GT : ComparisonFP<SETOGT, "gt ">;
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/ |
| D | Analysis.cpp | 205 case FCmpInst::FCMP_OGT: return ISD::SETOGT; in getFCmpCondCode()
229 case ISD::SETOGT: case ISD::SETUGT: return ISD::SETGT; in getFCmpCodeWithoutNaN()
|
| /external/llvm-project/llvm/lib/CodeGen/ |
| D | Analysis.cpp | 206 case FCmpInst::FCMP_OGT: return ISD::SETOGT; in getFCmpCondCode()
230 case ISD::SETOGT: case ISD::SETUGT: return ISD::SETGT; in getFCmpCodeWithoutNaN()
|
| /external/llvm-project/llvm/lib/Target/VE/ |
| D | VEISelDAGToDAG.cpp | 71 case ISD::SETOGT: in fpCondCode2Fcc()
|
| /external/llvm-project/llvm/lib/Target/AMDGPU/ |
| D | SIInsertSkips.cpp | 282 case ISD::SETOGT: in kill()
|
| D | AMDGPUInstructions.td | 248 def COND_OGT : PatFrags<(ops), [(OtherVT SETOGT), (OtherVT SETGT)]>;
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/WebAssembly/ |
| D | WebAssemblyInstrFloat.td | 85 defm GT : ComparisonFP<SETOGT, "gt ", 0x5e, 0x64>;
|
| /external/llvm-project/llvm/lib/Target/WebAssembly/ |
| D | WebAssemblyInstrFloat.td | 85 defm GT : ComparisonFP<SETOGT, "gt ", 0x5e, 0x64>;
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
| D | SIInsertSkips.cpp | 199 case ISD::SETOGT: in kill()
|
| D | AMDGPUInstructions.td | 246 def COND_OGT : PatFrags<(ops), [(OtherVT SETOGT), (OtherVT SETGT)]>;
|
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | SelectionDAGDumper.cpp | 332 case ISD::SETOGT: return "setogt"; in getOperationName()
|
| /external/llvm/lib/Target/PowerPC/ |
| D | PPCISelDAGToDAG.cpp | 2105 case ISD::SETOGT: in getPredicateForSetCC()
2126 case ISD::SETOGT: in getCRIdxForSetCC()
2163 case ISD::SETOLT: CC = ISD::SETOGT; Swap = true; break; in getVCmpInst()
2172 case ISD::SETULE: CC = ISD::SETOGT; Negate = true; break; in getVCmpInst()
2186 case ISD::SETOGT: in getVCmpInst()
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/SelectionDAG/ |
| D | SelectionDAGDumper.cpp | 409 case ISD::SETOGT: return "setogt"; in getOperationName()
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/PowerPC/ |
| D | PPCISelDAGToDAG.cpp | 3808 case ISD::SETOGT: in SelectCC()
3835 case ISD::SETOGT: in SelectCC()
3876 case ISD::SETOGT: in getPredicateForSetCC()
3899 case ISD::SETOGT: in getCRIdxForSetCC()
3936 case ISD::SETOLT: CC = ISD::SETOGT; Swap = true; break; in getVCmpInst()
3945 case ISD::SETULE: CC = ISD::SETOGT; Negate = true; break; in getVCmpInst()
3959 case ISD::SETOGT: in getVCmpInst()
|
| D | PPCInstrQPX.td | 470 (setcc v4f64:$FRA, v4f64:$FRB, SETOGT))]>;
475 (setcc v4f32:$FRA, v4f32:$FRB, SETOGT))]>;
|
| /external/llvm-project/llvm/lib/Target/PowerPC/ |
| D | PPCISelDAGToDAG.cpp | 3774 case ISD::SETOGT: in SelectCC()
3801 case ISD::SETOGT: in SelectCC()
3847 case ISD::SETOGT: in getPredicateForSetCC()
3870 case ISD::SETOGT: in getCRIdxForSetCC()
3908 case ISD::SETOLT: CC = ISD::SETOGT; Swap = true; break; in getVCmpInst()
3917 case ISD::SETULE: CC = ISD::SETOGT; Negate = true; break; in getVCmpInst()
3931 case ISD::SETOGT: in getVCmpInst()
|
| /external/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| D | SelectionDAGDumper.cpp | 430 case ISD::SETOGT: return "setogt"; in getOperationName()
|
| /external/llvm/lib/Target/AMDGPU/ |
| D | AMDGPUInstructions.td | 96 [{return N->get() == ISD::SETOGT || N->get() == ISD::SETGT;}]
|
| D | AMDGPUISelLowering.cpp | 1012 case ISD::SETOGT: { in CombineFMinMaxLegacy()
1619 SDValue Lt0 = DAG.getSetCC(SL, SetCCVT, Src, Zero, ISD::SETOGT); in LowerFCEIL()
1714 SDValue Cond = DAG.getSetCC(SL, SetCCVT, Fabs, C2, ISD::SETOGT); in LowerFRINT()
|
| /external/llvm/include/llvm/Target/ |
| D | TargetSelectionDAG.td | 591 def SETOEQ : CondCode; def SETOGT : CondCode;
975 (setcc node:$lhs, node:$rhs, SETOGT)>;
|
| /external/llvm/lib/Target/Mips/ |
| D | MipsSEISelLowering.cpp | 192 setCondCodeAction(ISD::SETOGT, MVT::f32, Expand); in MipsSETargetLowering()
197 setCondCodeAction(ISD::SETOGT, MVT::f64, Expand); in MipsSETargetLowering()
324 setCondCodeAction(ISD::SETOGT, Ty, Expand); in addMSAFloatType()
|