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Searched refs:SETUGE (Results 1 – 25 of 130) sorted by relevance

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/external/llvm/include/llvm/CodeGen/
DISDOpcodes.h863 SETUGE, // 1 0 1 1 True if unordered, greater than, or equal enumerator
890 return Code == SETUGT || Code == SETUGE || Code == SETULT || Code == SETULE; in isUnsignedIntSetCC()
/external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/
DISDOpcodes.h1060 SETUGE, // 1 0 1 1 True if unordered, greater than, or equal enumerator
1087 return Code == SETUGT || Code == SETUGE || Code == SETULT || Code == SETULE; in isUnsignedIntSetCC()
/external/llvm-project/llvm/include/llvm/CodeGen/
DISDOpcodes.h1276 SETUGE, // 1 0 1 1 True if unordered, greater than, or equal enumerator
1303 return Code == SETUGT || Code == SETUGE || Code == SETULT || Code == SETULE; in isUnsignedIntSetCC()
/external/llvm-project/llvm/lib/Target/VE/
DVEISelDAGToDAG.cpp49 case ISD::SETUGE: in intCondCode2Icc()
93 case ISD::SETUGE: in fpCondCode2Fcc()
/external/llvm/lib/CodeGen/
DAnalysis.cpp175 case FCmpInst::FCMP_UGE: return ISD::SETUGE; in getFCmpCondCode()
191 case ISD::SETOGE: case ISD::SETUGE: return ISD::SETGE; in getFCmpCodeWithoutNaN()
206 case ICmpInst::ICMP_UGE: return ISD::SETUGE; in getICmpCondCode()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/
DAnalysis.cpp214 case FCmpInst::FCMP_UGE: return ISD::SETUGE; in getFCmpCondCode()
230 case ISD::SETOGE: case ISD::SETUGE: return ISD::SETGE; in getFCmpCodeWithoutNaN()
245 case ICmpInst::ICMP_UGE: return ISD::SETUGE; in getICmpCondCode()
/external/llvm-project/llvm/lib/CodeGen/
DAnalysis.cpp215 case FCmpInst::FCMP_UGE: return ISD::SETUGE; in getFCmpCondCode()
231 case ISD::SETOGE: case ISD::SETUGE: return ISD::SETGE; in getFCmpCodeWithoutNaN()
246 case ICmpInst::ICMP_UGE: return ISD::SETUGE; in getICmpCondCode()
/external/llvm/lib/Target/WebAssembly/
DWebAssemblyInstrInteger.td53 defm GE_U : ComparisonInt<SETUGE, "ge_u">;
/external/llvm/lib/Target/Hexagon/
DHexagonSelectCCInfo.td68 IntRegs:$fval, SETUGE)),
/external/llvm/lib/CodeGen/SelectionDAG/
DTargetLowering.cpp243 case ISD::SETUGE: in softenSetCCOperands()
1578 case ISD::SETUGE: in SimplifySetCC()
1601 case ISD::SETUGE: in SimplifySetCC()
1748 if (Cond == ISD::SETGE || Cond == ISD::SETUGE) { in SimplifySetCC()
1780 if ((Cond == ISD::SETGE || Cond == ISD::SETUGE) && C1 == MinVal) in SimplifySetCC()
1876 } else if (Cond == ISD::SETULT || Cond == ISD::SETUGE || in SimplifySetCC()
1889 NewCond = (Cond == ISD::SETULE) ? ISD::SETULT : ISD::SETUGE; in SimplifySetCC()
1963 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETUGE); in SimplifySetCC()
2163 case ISD::SETUGE: // X >=u Y --> X == 1 | Y == 0 --> ~Y | X in SimplifySetCC()
/external/llvm-project/llvm/lib/Target/AMDGPU/
DSIInsertSkips.cpp314 case ISD::SETUGE: in kill()
DAMDGPUISelLowering.cpp1424 case ISD::SETUGE: in combineFMinMaxLegacy()
1880 ISD::SETUGE); in LowerUDIVREM64()
1882 ISD::SETUGE); in LowerUDIVREM64()
1902 ISD::SETUGE); in LowerUDIVREM64()
1904 ISD::SETUGE); in LowerUDIVREM64()
1962 SDValue realBIT = DAG.getSelectCC(DL, REM, RHS, BIT, Zero, ISD::SETUGE); in LowerUDIVREM64()
1968 REM = DAG.getSelectCC(DL, REM, RHS, REM_sub, REM, ISD::SETUGE); in LowerUDIVREM64()
2016 SDValue Cond = DAG.getSetCC(DL, CCVT, R, Y, ISD::SETUGE); in LowerUDIVREM()
2023 Cond = DAG.getSetCC(DL, CCVT, R, Y, ISD::SETUGE); in LowerUDIVREM()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/WebAssembly/
DWebAssemblyInstrInteger.td83 defm GE_U : ComparisonInt<SETUGE, "ge_u", 0x4f, 0x5a>;
/external/llvm-project/llvm/lib/Target/WebAssembly/
DWebAssemblyInstrInteger.td83 defm GE_U : ComparisonInt<SETUGE, "ge_u", 0x4f, 0x5a>;
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/
DSIInsertSkips.cpp231 case ISD::SETUGE: in kill()
DAMDGPUISelLowering.cpp1305 case ISD::SETUGE: in combineFMinMaxLegacy()
1751 ISD::SETUGE); in LowerUDIVREM64()
1753 ISD::SETUGE); in LowerUDIVREM64()
1773 ISD::SETUGE); in LowerUDIVREM64()
1775 ISD::SETUGE); in LowerUDIVREM64()
1833 SDValue realBIT = DAG.getSelectCC(DL, REM, RHS, BIT, Zero, ISD::SETUGE); in LowerUDIVREM64()
1839 REM = DAG.getSelectCC(DL, REM, RHS, REM_sub, REM, ISD::SETUGE); in LowerUDIVREM64()
1912 ISD::SETUGE); in LowerUDIVREM()
1918 ISD::SETUGE); in LowerUDIVREM()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/PowerPC/
DPPCInstrQPX.td1007 def : Pat<(setcc v4f64:$FRA, v4f64:$FRB, SETUGE),
1054 def : Pat<(setcc v4f32:$FRA, v4f32:$FRB, SETUGE),
1126 def : Pat<(v4f64 (selectcc i1:$lhs, i1:$rhs, v4f64:$tval, v4f64:$fval, SETUGE)),
1147 def : Pat<(v4f32 (selectcc i1:$lhs, i1:$rhs, v4f32:$tval, v4f32:$fval, SETUGE)),
1168 def : Pat<(v4i1 (selectcc i1:$lhs, i1:$rhs, v4i1:$tval, v4i1:$fval, SETUGE)),
DPPCInstrInfo.td3424 def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETUGE)),
3707 defm : CRNotPat<(i1 (setcc i32:$s1, immZExt16:$imm, SETUGE)),
3724 defm : CRNotPat<(i1 (setcc i32:$s1, i32:$s2, SETUGE)),
3736 defm : CRNotPat<(i1 (setcc i64:$s1, immZExt16:$imm, SETUGE)),
3753 defm : CRNotPat<(i1 (setcc i64:$s1, i64:$s2, SETUGE)),
3766 defm : CRNotPat<(i1 (setcc f32:$s1, f32:$s2, SETUGE)),
3782 defm : CRNotPat<(i1 (setcc f64:$s1, f64:$s2, SETUGE)),
3798 defm : CRNotPat<(i1 (setcc f128:$s1, f128:$s2, SETUGE)),
3882 defm : CRNotPat<(i1 (setcc f32:$s1, f32:$s2, SETUGE)),
3909 defm : CRNotPat<(i1 (setcc f64:$s1, f64:$s2, SETUGE)),
[all …]
DPPCISelDAGToDAG.cpp3036 case ISD::SETUGE: in get32BitZExtCompare()
3209 case ISD::SETUGE: in get32BitSExtCompare()
3368 case ISD::SETUGE: in get64BitZExtCompare()
3531 case ISD::SETUGE: in get64BitSExtCompare()
3803 case ISD::SETUGE: in SelectCC()
3830 case ISD::SETUGE: in SelectCC()
3879 case ISD::SETUGE: in getPredicateForSetCC()
3904 case ISD::SETUGE: in getCRIdxForSetCC()
3937 case ISD::SETUGE: CC = ISD::SETULE; Swap = true; break; in getVCmpInst()
3981 case ISD::SETUGE: CC = ISD::SETULE; Swap = true; break; in getVCmpInst()
/external/llvm/lib/Target/PowerPC/
DPPCInstrQPX.td1010 def : Pat<(setcc v4f64:$FRA, v4f64:$FRB, SETUGE),
1057 def : Pat<(setcc v4f32:$FRA, v4f32:$FRB, SETUGE),
1129 def : Pat<(v4f64 (selectcc i1:$lhs, i1:$rhs, v4f64:$tval, v4f64:$fval, SETUGE)),
1150 def : Pat<(v4f32 (selectcc i1:$lhs, i1:$rhs, v4f32:$tval, v4f32:$fval, SETUGE)),
1171 def : Pat<(v4i1 (selectcc i1:$lhs, i1:$rhs, v4i1:$tval, v4i1:$fval, SETUGE)),
/external/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/PowerPC/
DPPCGenDAGISel.inc4248 /* 9335*/ OPC_CheckChild2CondCode, ISD::SETUGE,
4266 …:[i32] }:$s1, (imm:{ *:[i32] })<<P:Predicate_immZExt16>><<X:LO16>>:$imm, SETUGE:{ *:[Other] })) - …
4286 …:[i32] }:$s1, (imm:{ *:[i32] })<<P:Predicate_immZExt16>><<X:LO16>>:$imm, SETUGE:{ *:[Other] })) - …
4564 /* 10191*/ OPC_CheckChild2CondCode, ISD::SETUGE,
4581 …:{ *:[i32] } (setcc:{ *:[i1] } i32:{ *:[i32] }:$s1, i32:{ *:[i32] }:$s2, SETUGE:{ *:[Other] })) - …
4600 …:{ *:[i64] } (setcc:{ *:[i1] } i32:{ *:[i32] }:$s1, i32:{ *:[i32] }:$s2, SETUGE:{ *:[Other] })) - …
5081 /* 11564*/ OPC_CheckChild2CondCode, ISD::SETUGE,
5099 …:[i64] }:$s1, (imm:{ *:[i64] })<<P:Predicate_immZExt16>><<X:LO16>>:$imm, SETUGE:{ *:[Other] })) - …
5119 …:[i64] }:$s1, (imm:{ *:[i64] })<<P:Predicate_immZExt16>><<X:LO16>>:$imm, SETUGE:{ *:[Other] })) - …
5398 /* 12422*/ OPC_CheckChild2CondCode, ISD::SETUGE,
[all …]
/external/llvm-project/llvm/lib/Target/PowerPC/
DPPCISelDAGToDAG.cpp2996 case ISD::SETUGE: in get32BitZExtCompare()
3169 case ISD::SETUGE: in get32BitSExtCompare()
3328 case ISD::SETUGE: in get64BitZExtCompare()
3491 case ISD::SETUGE: in get64BitSExtCompare()
3769 case ISD::SETUGE: in SelectCC()
3796 case ISD::SETUGE: in SelectCC()
3850 case ISD::SETUGE: in getPredicateForSetCC()
3875 case ISD::SETUGE: in getCRIdxForSetCC()
3909 case ISD::SETUGE: CC = ISD::SETULE; Swap = true; break; in getVCmpInst()
3953 case ISD::SETUGE: CC = ISD::SETULE; Swap = true; break; in getVCmpInst()
/external/llvm-project/llvm/lib/Target/AVR/
DAVRISelLowering.cpp433 case ISD::SETUGE: in intCCToAVRCC()
516 CC = ISD::SETUGE; in getAVRCmp()
524 CC = ISD::SETUGE; in getAVRCmp()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AVR/
DAVRISelLowering.cpp434 case ISD::SETUGE: in intCCToAVRCC()
517 CC = ISD::SETUGE; in getAVRCmp()
525 CC = ISD::SETUGE; in getAVRCmp()
/external/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/Mips/
DMipsGenDAGISel.inc1992 /* 3529*/ OPC_CheckChild2CondCode, ISD::SETUGE,
2006 …GPR32:{ *:[i32] }:$lhs, (imm:{ *:[i32] })<<P:Predicate_immSExt16>>:$rhs, SETUGE:{ *:[Other] }), (b…
2072 /* 3687*/ OPC_CheckChild2CondCode, ISD::SETUGE,
2086 …GPR32:{ *:[i32] }:$lhs, (imm:{ *:[i32] })<<P:Predicate_immSExt16>>:$rhs, SETUGE:{ *:[Other] }), (b…
2151 /* 3841*/ OPC_CheckChild2CondCode, ISD::SETUGE,
2164 …GPR32:{ *:[i32] }:$lhs, (imm:{ *:[i32] })<<P:Predicate_immSExt16>>:$rhs, SETUGE:{ *:[Other] }), (b…
2348 /* 4183*/ OPC_CheckChild2CondCode, ISD::SETUGE,
2362 …rcond (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETUGE:{ *:[Other] }), (b…
2416 /* 4319*/ OPC_CheckChild2CondCode, ISD::SETUGE,
2430 …rcond (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETUGE:{ *:[Other] }), (b…
[all …]

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