| /external/llvm/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 864 SETULT, // 1 1 0 0 True if unordered or less than enumerator
890 return Code == SETUGT || Code == SETUGE || Code == SETULT || Code == SETULE; in isUnsignedIntSetCC()
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| /external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 1061 SETULT, // 1 1 0 0 True if unordered or less than enumerator
1087 return Code == SETUGT || Code == SETUGE || Code == SETULT || Code == SETULE; in isUnsignedIntSetCC()
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| /external/llvm-project/llvm/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 1277 SETULT, // 1 1 0 0 True if unordered or less than enumerator
1303 return Code == SETUGT || Code == SETUGE || Code == SETULT || Code == SETULE; in isUnsignedIntSetCC()
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| /external/llvm-project/llvm/lib/Target/VE/ |
| D | VEISelDAGToDAG.cpp | 43 case ISD::SETULT: in intCondCode2Icc()
87 case ISD::SETULT: in fpCondCode2Fcc()
|
| /external/llvm/lib/CodeGen/ |
| D | Analysis.cpp | 176 case FCmpInst::FCMP_ULT: return ISD::SETULT; in getFCmpCondCode()
188 case ISD::SETOLT: case ISD::SETULT: return ISD::SETLT; in getFCmpCodeWithoutNaN()
208 case ICmpInst::ICMP_ULT: return ISD::SETULT; in getICmpCondCode()
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/ |
| D | Analysis.cpp | 215 case FCmpInst::FCMP_ULT: return ISD::SETULT; in getFCmpCondCode()
227 case ISD::SETOLT: case ISD::SETULT: return ISD::SETLT; in getFCmpCodeWithoutNaN()
247 case ICmpInst::ICMP_ULT: return ISD::SETULT; in getICmpCondCode()
|
| /external/llvm-project/llvm/lib/CodeGen/ |
| D | Analysis.cpp | 216 case FCmpInst::FCMP_ULT: return ISD::SETULT; in getFCmpCondCode()
228 case ISD::SETOLT: case ISD::SETULT: return ISD::SETLT; in getFCmpCodeWithoutNaN()
248 case ICmpInst::ICMP_ULT: return ISD::SETULT; in getICmpCondCode()
|
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | TargetLowering.cpp | 228 case ISD::SETULT: in softenSetCCOperands()
1412 if ((Cond == ISD::SETULT && C1 == 2) || (Cond == ISD::SETUGT && C1 == 1)){ in SimplifySetCC()
1416 ISD::CondCode CC = Cond == ISD::SETULT ? ISD::SETEQ : ISD::SETNE; in SimplifySetCC()
1580 case ISD::SETULT: in SimplifySetCC()
1602 case ISD::SETULT: in SimplifySetCC()
1767 ISD::CondCode NewCC = (Cond == ISD::SETLE) ? ISD::SETLT : ISD::SETULT; in SimplifySetCC()
1778 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal) in SimplifySetCC()
1791 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MaxVal) in SimplifySetCC()
1795 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal+1) in SimplifySetCC()
1816 if (Cond == ISD::SETULT && in SimplifySetCC()
[all …]
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| D | LegalizeIntegerTypes.cpp | 973 case ISD::SETULT: in PromoteSetCCOperands()
1617 Amt, NVBitsNode, ISD::SETULT); in ExpandShiftWithUnknownAmountBit()
1687 return std::make_pair(ISD::SETULT, ISD::UMIN); in getExpandedMinMaxOps()
1796 ISD::SETULT); in ExpandIntRes_ADDSUB()
1801 ISD::SETULT); in ExpandIntRes_ADDSUB()
1810 LoOps[0], LoOps[1], ISD::SETULT); in ExpandIntRes_ADDSUB()
2536 ISD::SETULT : ISD::SETUGT); in ExpandIntRes_UADDSUBO()
2834 case ISD::SETULT: LowCC = ISD::SETULT; break; in IntegerExpandSetCCOperands()
2876 CCCode == ISD::SETUGT || CCCode == ISD::SETULT))) { in IntegerExpandSetCCOperands()
2903 case ISD::SETUGT: CCCode = ISD::SETULT; FlipOperands = true; break; in IntegerExpandSetCCOperands()
|
| /external/llvm/lib/Target/WebAssembly/ |
| D | WebAssemblyInstrInteger.td | 48 defm LT_U : ComparisonInt<SETULT, "lt_u">;
|
| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonSelectCCInfo.td | 37 IntRegs:$fval, SETULT)),
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/PowerPC/ |
| D | PPCISelDAGToDAG.cpp | 3061 case ISD::SETULT: { in get32BitZExtCompare()
3234 case ISD::SETULT: { in get32BitSExtCompare()
3390 case ISD::SETULT: { in get64BitZExtCompare()
3553 case ISD::SETULT: { in get64BitSExtCompare()
3802 case ISD::SETULT: in SelectCC()
3829 case ISD::SETULT: in SelectCC()
3885 case ISD::SETULT: return PPC::PRED_LT; in getPredicateForSetCC()
3917 case ISD::SETULT: return 0; in getCRIdxForSetCC()
3938 case ISD::SETUGT: CC = ISD::SETULT; Swap = true; break; in getVCmpInst()
3946 case ISD::SETULT: CC = ISD::SETOGE; Negate = true; break; in getVCmpInst()
[all …]
|
| /external/llvm-project/llvm/lib/Target/PowerPC/ |
| D | PPCISelDAGToDAG.cpp | 3021 case ISD::SETULT: { in get32BitZExtCompare()
3194 case ISD::SETULT: { in get32BitSExtCompare()
3350 case ISD::SETULT: { in get64BitZExtCompare()
3513 case ISD::SETULT: { in get64BitSExtCompare()
3768 case ISD::SETULT: in SelectCC()
3795 case ISD::SETULT: in SelectCC()
3856 case ISD::SETULT: return PPC::PRED_LT; in getPredicateForSetCC()
3888 case ISD::SETULT: return 0; in getCRIdxForSetCC()
3910 case ISD::SETUGT: CC = ISD::SETULT; Swap = true; break; in getVCmpInst()
3918 case ISD::SETULT: CC = ISD::SETOGE; Negate = true; break; in getVCmpInst()
[all …]
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/BPF/ |
| D | BPFISelLowering.cpp | 488 case ISD::SETULT: in NegateCC()
694 SET_NEWCC(SETULT, JULT); in EmitInstrWithCustomInserter()
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
| D | R600ISelLowering.cpp | 136 setCondCodeAction(ISD::SETULT, MVT::f32, Expand); in R600TargetLowering()
142 setCondCodeAction(ISD::SETULT, MVT::i32, Expand); in R600TargetLowering()
821 Hi = DAG.getSelectCC(DL, Shift, Width, HiSmall, HiBig, ISD::SETULT); in LowerSHLParts()
822 Lo = DAG.getSelectCC(DL, Shift, Width, LoSmall, LoBig, ISD::SETULT); in LowerSHLParts()
859 Hi = DAG.getSelectCC(DL, Shift, Width, HiSmall, HiBig, ISD::SETULT); in LowerSRXParts()
860 Lo = DAG.getSelectCC(DL, Shift, Width, LoSmall, LoBig, ISD::SETULT); in LowerSRXParts()
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| D | SIInsertSkips.cpp | 234 case ISD::SETULT: in kill()
|
| /external/llvm-project/llvm/lib/Target/AMDGPU/ |
| D | R600ISelLowering.cpp | 136 setCondCodeAction(ISD::SETULT, MVT::f32, Expand); in R600TargetLowering()
142 setCondCodeAction(ISD::SETULT, MVT::i32, Expand); in R600TargetLowering()
826 Hi = DAG.getSelectCC(DL, Shift, Width, HiSmall, HiBig, ISD::SETULT); in LowerSHLParts()
827 Lo = DAG.getSelectCC(DL, Shift, Width, LoSmall, LoBig, ISD::SETULT); in LowerSHLParts()
864 Hi = DAG.getSelectCC(DL, Shift, Width, HiSmall, HiBig, ISD::SETULT); in LowerSRXParts()
865 Lo = DAG.getSelectCC(DL, Shift, Width, LoSmall, LoBig, ISD::SETULT); in LowerSRXParts()
|
| D | SIInsertSkips.cpp | 317 case ISD::SETULT: in kill()
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/WebAssembly/ |
| D | WebAssemblyInstrInteger.td | 77 defm LT_U : ComparisonInt<SETULT, "lt_u", 0x49, 0x54>;
|
| /external/llvm-project/llvm/lib/Target/WebAssembly/ |
| D | WebAssemblyInstrInteger.td | 77 defm LT_U : ComparisonInt<SETULT, "lt_u", 0x49, 0x54>;
|
| /external/llvm-project/llvm/lib/Target/BPF/ |
| D | BPFISelLowering.cpp | 521 case ISD::SETULT: in NegateCC()
733 SET_NEWCC(SETULT, JULT); in EmitInstrWithCustomInserter()
|
| /external/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| D | TargetLowering.cpp | 363 case ISD::SETULT: in softenSetCCOperands()
3205 if (Cond == ISD::CondCode::SETULT) { in optimizeSetCCOfSignedTruncationCheck()
3406 if (Cond == ISD::SETULT || Cond == ISD::SETUGT) { in simplifySetCCWithCTPOP()
3408 if (C1.ugt(CostLimit + (Cond == ISD::SETULT))) in simplifySetCCWithCTPOP()
3410 if (C1 == 0 && (Cond == ISD::SETULT)) in simplifySetCCWithCTPOP()
3413 unsigned Passes = C1.getLimitedValue() - (Cond == ISD::SETULT); in simplifySetCCWithCTPOP()
3421 ISD::CondCode CC = Cond == ISD::SETULT ? ISD::SETEQ : ISD::SETNE; in simplifySetCCWithCTPOP()
3679 case ISD::SETULT: in SimplifySetCC()
3702 case ISD::SETULT: in SimplifySetCC()
3904 ISD::CondCode NewCC = (Cond == ISD::SETLE) ? ISD::SETLT : ISD::SETULT; in SimplifySetCC()
[all …]
|
| /external/llvm/lib/Target/AMDGPU/ |
| D | R600ISelLowering.cpp | 99 setCondCodeAction(ISD::SETULT, MVT::f32, Expand); in R600TargetLowering()
105 setCondCodeAction(ISD::SETULT, MVT::i32, Expand); in R600TargetLowering()
995 Hi = DAG.getSelectCC(DL, Shift, Width, HiSmall, HiBig, ISD::SETULT); in LowerSHLParts()
996 Lo = DAG.getSelectCC(DL, Shift, Width, LoSmall, LoBig, ISD::SETULT); in LowerSHLParts()
1033 Hi = DAG.getSelectCC(DL, Shift, Width, HiSmall, HiBig, ISD::SETULT); in LowerSRXParts()
1034 Lo = DAG.getSelectCC(DL, Shift, Width, LoSmall, LoBig, ISD::SETULT); in LowerSRXParts()
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/SelectionDAG/ |
| D | LegalizeIntegerTypes.cpp | 1382 case ISD::SETULT: in PromoteSetCCOperands()
2145 Amt, NVBitsNode, ISD::SETULT); in ExpandShiftWithUnknownAmountBit()
2215 return std::make_pair(ISD::SETULT, ISD::UMIN); in getExpandedMinMaxOps()
2345 ISD::SETULT); in ExpandIntRes_ADDSUB()
2357 ISD::SETULT); in ExpandIntRes_ADDSUB()
2366 LoOps[0], LoOps[1], ISD::SETULT); in ExpandIntRes_ADDSUB()
2439 Cond = ISD::SETULT; in ExpandIntRes_UADDSUBO()
3193 SDValue HLULT = DAG.getSetCC(dl, BoolNVT, ResultHL, HLHiMask, ISD::SETULT); in ExpandIntRes_MULFIX()
3846 case ISD::SETULT: LowCC = ISD::SETULT; break; in IntegerExpandSetCCOperands()
3916 case ISD::SETUGT: CCCode = ISD::SETULT; FlipOperands = true; break; in IntegerExpandSetCCOperands()
|
| D | TargetLowering.cpp | 371 case ISD::SETULT: in softenSetCCOperands()
2939 if (Cond == ISD::CondCode::SETULT) { in optimizeSetCCOfSignedTruncationCheck()
3189 if ((Cond == ISD::SETULT && C1 == 2) || (Cond == ISD::SETUGT && C1 == 1)){ in SimplifySetCC()
3193 ISD::CondCode CC = Cond == ISD::SETULT ? ISD::SETEQ : ISD::SETNE; in SimplifySetCC()
3374 case ISD::SETULT: in SimplifySetCC()
3397 case ISD::SETULT: in SimplifySetCC()
3599 ISD::CondCode NewCC = (Cond == ISD::SETLE) ? ISD::SETLT : ISD::SETULT; in SimplifySetCC()
3611 if (Cond == ISD::SETLT || Cond == ISD::SETULT) { in SimplifySetCC()
3667 if (Cond == ISD::SETULT && in SimplifySetCC()
3733 } else if (Cond == ISD::SETULT || Cond == ISD::SETUGE || in SimplifySetCC()
[all …]
|