| /external/llvm-project/llvm/lib/Target/X86/ |
| D | X86LoadValueInjectionLoadHardening.cpp | 772 MI.getOpcode() == X86::SFENCE || MI.getOpcode() == X86::LFENCE) in instrUsesRegToAccessMemory()
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| D | X86SchedBroadwell.td | 733 def: InstRW<[BWWriteResGroup18], (instrs SFENCE)>;
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| D | X86SchedHaswell.td | 1042 def: InstRW<[HWWriteResGroup19], (instrs SFENCE)>;
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| D | X86SchedSkylakeClient.td | 728 def: InstRW<[SKLWriteResGroup21], (instrs SFENCE)>;
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| D | X86SchedSkylakeServer.td | 754 def: InstRW<[SKXWriteResGroup21], (instrs SFENCE)>;
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| D | X86InstrSSE.td | 3195 def SFENCE : I<0xAE, MRM7X, (outs), (ins), "sfence", [(int_x86_sse_sfence)]>,
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/ |
| D | X86SchedBroadwell.td | 730 def: InstRW<[BWWriteResGroup18], (instrs SFENCE)>;
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| D | X86SchedSkylakeClient.td | 725 def: InstRW<[SKLWriteResGroup21], (instrs SFENCE)>;
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| D | X86SchedHaswell.td | 1039 def: InstRW<[HWWriteResGroup19], (instrs SFENCE)>;
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| D | X86SchedSkylakeServer.td | 749 def: InstRW<[SKXWriteResGroup21], (instrs SFENCE)>;
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| D | X86InstrSSE.td | 3190 def SFENCE : I<0xAE, MRM_F8, (outs), (ins), "sfence", [(int_x86_sse_sfence)]>,
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| /external/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/X86/ |
| D | X86GenSubtargetInfo.inc | 6526 {DBGFIELD("SFENCE") 1, false, false, 6, 2, 1, 1, 0, 0}, // #837
7903 {DBGFIELD("SFENCE") 1, false, false, 248, 2, 1, 1, 0, 0}, // #837
9280 {DBGFIELD("SFENCE") 2, false, false, 727, 3, 3, 1, 0, 0}, // #837
10657 {DBGFIELD("SFENCE") 1, false, false, 135, 2, 1, 1, 0, 0}, // #837
12034 {DBGFIELD("SFENCE") 2, false, false, 727, 3, 3, 1, 0, 0}, // #837
13411 {DBGFIELD("SFENCE") 1, false, false, 3711, 3, 1, 1, 0, 0}, // #837
14788 {DBGFIELD("SFENCE") 2, false, false, 727, 3, 3, 1, 0, 0}, // #837
16165 {DBGFIELD("SFENCE") 1, false, false, 129, 1, 1, 1, 0, 0}, // #837
17542 {DBGFIELD("SFENCE") 2, false, false, 727, 3, 3, 1, 0, 0}, // #837
18919 {DBGFIELD("SFENCE") 1, false, false, 2, 1, 1, 1, 0, 0}, // #837
[all …]
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| D | X86GenGlobalISel.inc | 9525 // (intrinsic_void 7257:{ *:[iPTR] }) => (SFENCE)
9526 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::SFENCE,
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| D | X86GenAsmWriter.inc | 4266 15537U, // SFENCE
19517 0U, // SFENCE
34768 0U, // SFENCE
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| D | X86GenDisassemblerTables.inc | 17763 /* SFENCE */
79332 0xa27, /* SFENCE */
80349 0xa27, /* SFENCE */
80985 0xa27, /* SFENCE */
81151 0xa27, /* SFENCE */
81608 0xa27, /* SFENCE */
81722 0xa27, /* SFENCE */
81818 0xa27, /* SFENCE */
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| D | X86GenAsmWriter1.inc | 3975 12302U, // SFENCE
19226 0U, // SFENCE
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| D | X86GenAsmMatcher.inc | 10259 { 7230 /* sfence */, X86::SFENCE, Convert_NoOperands, AMFBS_None, { }, },
24823 { 7230 /* sfence */, X86::SFENCE, Convert_NoOperands, AMFBS_None, { }, },
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| D | X86GenInstrInfo.inc | 2614 SFENCE = 2599,
16114 SFENCE = 837,
20299 …ledSideEffects), 0x2b80002078ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #2599 = SFENCE
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| /external/mesa3d/src/mesa/x86/ |
| D | assyntax.h | 1701 #define SFENCE sfence macro
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| /external/capstone/arch/X86/ |
| D | X86GenAsmWriter1.inc | 2675 10301U, // SFENCE
11532 0U, // SFENCE
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| D | X86GenAsmWriter.inc | 2675 12897U, // SFENCE
11532 0U, // SFENCE
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| D | X86GenDisassemblerTables.inc | 20359 /* SFENCE */
64438 0xa62, /* SFENCE */
65955 0xa62, /* SFENCE */
66287 0xa62, /* SFENCE */
66369 0xa62, /* SFENCE */
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| /external/llvm/lib/Target/X86/ |
| D | X86InstrSSE.td | 3682 def SFENCE : I<0xAE, MRM_F8, (outs), (ins),
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