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Searched refs:SHADER_OPCODE_TEX (Results 1 – 13 of 13) sorted by relevance

/external/mesa3d/src/intel/compiler/
Dbrw_shader.cpp223 case SHADER_OPCODE_TEX: in brw_instruction_name()
878 return (opcode == SHADER_OPCODE_TEX || in is_tex()
Dbrw_ir_vec4.h343 case SHADER_OPCODE_TEX: in reads_g0_implicitly()
Dtest_vec4_cmod_propagation.cpp373 bld.emit(SHADER_OPCODE_TEX, dest, src2) in TEST_F()
399 EXPECT_EQ(SHADER_OPCODE_TEX, instruction(block0, 1)->opcode); in TEST_F()
Dtest_fs_saturate_propagation.cpp651 bld.emit(SHADER_OPCODE_TEX, dst0, src2) in TEST_F()
676 EXPECT_EQ(SHADER_OPCODE_TEX, instruction(block0, 1)->opcode); in TEST_F()
Dbrw_eu_defines.h338 SHADER_OPCODE_TEX, enumerator
Dbrw_vec4_generator.cpp122 case SHADER_OPCODE_TEX: in generate_tex()
177 case SHADER_OPCODE_TEX: in generate_tex()
1749 case SHADER_OPCODE_TEX: in generate_code()
Dbrw_fs_generator.cpp1112 case SHADER_OPCODE_TEX: in generate_tex()
1162 case SHADER_OPCODE_TEX: in generate_tex()
2284 case SHADER_OPCODE_TEX: in generate_code()
Dbrw_fs.cpp270 case SHADER_OPCODE_TEX: in is_control_source()
1158 case SHADER_OPCODE_TEX: in implied_mrf_writes()
4688 (op == SHADER_OPCODE_TEX && bld.dispatch_width() == 8))) { in lower_sampler_logical_send_gen4()
4744 if (op == SHADER_OPCODE_TEX && bld.dispatch_width() == 8) { in lower_sampler_logical_send_gen4()
4878 case SHADER_OPCODE_TEX: in sampler_msg_type()
6058 lower_sampler_logical_send(ibld, inst, SHADER_OPCODE_TEX); in lower_logical_sends()
6455 if (inst->opcode != SHADER_OPCODE_TEX && in get_sampler_lowered_simd_width()
Dbrw_ir_performance.cpp888 case SHADER_OPCODE_TEX: in instruction_desc()
Dtest_fs_cmod_propagation.cpp410 bld.emit(SHADER_OPCODE_TEX, dest, src2) in TEST_F()
435 EXPECT_EQ(SHADER_OPCODE_TEX, instruction(block0, 1)->opcode); in TEST_F()
Dbrw_schedule_instructions.cpp241 case SHADER_OPCODE_TEX: in set_latency_gen7()
Dbrw_vec4.cpp366 case SHADER_OPCODE_TEX: in implied_mrf_writes()
/external/igt-gpu-tools/assembler/
Dbrw_defines.h722 SHADER_OPCODE_TEX, enumerator