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Searched refs:SHADER_OPCODE_TXL (Results 1 – 11 of 11) sorted by relevance

/external/mesa3d/src/intel/compiler/
Dbrw_shader.cpp237 case SHADER_OPCODE_TXL: in brw_instruction_name()
887 opcode == SHADER_OPCODE_TXL || in is_tex()
Dbrw_ir_vec4.h344 case SHADER_OPCODE_TXL: in reads_g0_implicitly()
Dbrw_eu_defines.h345 SHADER_OPCODE_TXL, enumerator
Dbrw_vec4_generator.cpp123 case SHADER_OPCODE_TXL: in generate_tex()
178 case SHADER_OPCODE_TXL: in generate_tex()
1755 case SHADER_OPCODE_TXL: in generate_code()
Dbrw_fs_generator.cpp1126 case SHADER_OPCODE_TXL: in generate_tex()
1194 case SHADER_OPCODE_TXL: in generate_tex()
2289 case SHADER_OPCODE_TXL: in generate_code()
Dbrw_fs.cpp279 case SHADER_OPCODE_TXL: in is_control_source()
1166 case SHADER_OPCODE_TXL: in implied_mrf_writes()
4669 const bool has_lod = (op == SHADER_OPCODE_TXL || op == FS_OPCODE_TXB || in lower_sampler_logical_send_gen4()
4804 case SHADER_OPCODE_TXL: in lower_sampler_logical_send_gen5()
4884 case SHADER_OPCODE_TXL: in sampler_msg_type()
5063 case SHADER_OPCODE_TXL: in lower_sampler_logical_send_gen7()
5064 if (devinfo->gen >= 9 && op == SHADER_OPCODE_TXL && lod.is_zero()) { in lower_sampler_logical_send_gen7()
6070 lower_sampler_logical_send(ibld, inst, SHADER_OPCODE_TXL); in lower_logical_sends()
6476 (inst->opcode == SHADER_OPCODE_TXL || in get_sampler_lowered_simd_width()
Dbrw_vec4_visitor.cpp845 case ir_tex: opcode = SHADER_OPCODE_TXL; break; in emit_texture()
846 case ir_txl: opcode = SHADER_OPCODE_TXL; break; in emit_texture()
Dbrw_ir_performance.cpp893 case SHADER_OPCODE_TXL: in instruction_desc()
Dbrw_schedule_instructions.cpp245 case SHADER_OPCODE_TXL: in set_latency_gen7()
Dbrw_vec4.cpp367 case SHADER_OPCODE_TXL: in implied_mrf_writes()
/external/igt-gpu-tools/assembler/
Dbrw_defines.h725 SHADER_OPCODE_TXL, enumerator