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Searched refs:SIGN_EXTEND_INREG (Results 1 – 25 of 113) sorted by relevance

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/external/llvm-project/llvm/test/CodeGen/WebAssembly/
Dsimd-nonconst-sext.ll3 ; A regression test for a bug in the lowering of SIGN_EXTEND_INREG
Dsignext-inreg.ll57 ; No SIGN_EXTEND_INREG is needed for 32->64 extension.
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/
DR600ISelLowering.cpp186 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand); in R600TargetLowering()
188 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i1, Expand); in R600TargetLowering()
189 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i1, Expand); in R600TargetLowering()
192 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Expand); in R600TargetLowering()
193 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i8, Expand); in R600TargetLowering()
194 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i8, Expand); in R600TargetLowering()
197 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand); in R600TargetLowering()
198 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i16, Expand); in R600TargetLowering()
199 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i16, Expand); in R600TargetLowering()
201 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal); in R600TargetLowering()
[all …]
/external/llvm-project/llvm/lib/Target/AMDGPU/
DR600ISelLowering.cpp186 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand); in R600TargetLowering()
188 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i1, Expand); in R600TargetLowering()
189 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i1, Expand); in R600TargetLowering()
192 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Expand); in R600TargetLowering()
193 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i8, Expand); in R600TargetLowering()
194 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i8, Expand); in R600TargetLowering()
197 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand); in R600TargetLowering()
198 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i16, Expand); in R600TargetLowering()
199 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i16, Expand); in R600TargetLowering()
201 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal); in R600TargetLowering()
[all …]
/external/llvm/lib/Target/AMDGPU/
DR600ISelLowering.cpp143 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand); in R600TargetLowering()
145 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i1, Expand); in R600TargetLowering()
146 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i1, Expand); in R600TargetLowering()
149 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Expand); in R600TargetLowering()
150 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i8, Expand); in R600TargetLowering()
151 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i8, Expand); in R600TargetLowering()
154 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand); in R600TargetLowering()
155 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i16, Expand); in R600TargetLowering()
156 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i16, Expand); in R600TargetLowering()
158 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal); in R600TargetLowering()
[all …]
DSIISelLowering.cpp118 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i1, Custom); in SITargetLowering()
119 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i1, Custom); in SITargetLowering()
120 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i8, Custom); in SITargetLowering()
121 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i8, Custom); in SITargetLowering()
122 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i16, Custom); in SITargetLowering()
123 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i16, Custom); in SITargetLowering()
124 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::Other, Custom); in SITargetLowering()
/external/llvm/lib/Target/BPF/
DBPFISelLowering.cpp107 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand); in BPFTargetLowering()
108 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Expand); in BPFTargetLowering()
109 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand); in BPFTargetLowering()
110 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Expand); in BPFTargetLowering()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/BPF/
DBPFISelLowering.cpp117 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand); in BPFTargetLowering()
118 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Expand); in BPFTargetLowering()
119 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand); in BPFTargetLowering()
120 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Expand); in BPFTargetLowering()
/external/llvm-project/llvm/lib/Target/BPF/
DBPFISelLowering.cpp116 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand); in BPFTargetLowering()
117 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Expand); in BPFTargetLowering()
118 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand); in BPFTargetLowering()
119 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Expand); in BPFTargetLowering()
/external/llvm/include/llvm/CodeGen/
DISDOpcodes.h413 SIGN_EXTEND_INREG, enumerator
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/WebAssembly/
DWebAssemblyISelLowering.cpp214 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand); in WebAssemblyTargetLowering()
219 setOperationAction(ISD::SIGN_EXTEND_INREG, T, Action); in WebAssemblyTargetLowering()
222 setOperationAction(ISD::SIGN_EXTEND_INREG, T, Expand); in WebAssemblyTargetLowering()
972 case ISD::SIGN_EXTEND_INREG: in ReplaceNodeResults()
1024 case ISD::SIGN_EXTEND_INREG: in LowerOperation()
1301 return DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, Op.getValueType(), in LowerSIGN_EXTEND_INREG()
1341 if (IndexExt->getOpcode() != ISD::SIGN_EXTEND_INREG) in LowerBUILD_VECTOR()
/external/llvm-project/llvm/lib/Target/WebAssembly/
DWebAssemblyISelLowering.cpp201 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand); in WebAssemblyTargetLowering()
206 setOperationAction(ISD::SIGN_EXTEND_INREG, T, Action); in WebAssemblyTargetLowering()
209 setOperationAction(ISD::SIGN_EXTEND_INREG, T, Expand); in WebAssemblyTargetLowering()
1157 case ISD::SIGN_EXTEND_INREG: in ReplaceNodeResults()
1211 case ISD::SIGN_EXTEND_INREG: in LowerOperation()
1554 return DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, Op.getValueType(), NewExtract, in LowerSIGN_EXTEND_INREG()
1591 if (IndexExt->getOpcode() != ISD::SIGN_EXTEND_INREG) in LowerBUILD_VECTOR()
1852 ShiftedValue = DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, MVT::i32, in unrollVectorShift()
/external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/
DISDOpcodes.h547 SIGN_EXTEND_INREG, enumerator
/external/llvm-project/llvm/include/llvm/CodeGen/
DISDOpcodes.h696 SIGN_EXTEND_INREG, enumerator
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/
DHexagonISelLoweringHVX.cpp137 setOperationAction(ISD::SIGN_EXTEND_INREG, T, Custom); in initializeHVXLowering()
199 setOperationAction(ISD::SIGN_EXTEND_INREG, T, Legal); in initializeHVXLowering()
202 setOperationAction(ISD::SIGN_EXTEND_INREG, T, Legal); in initializeHVXLowering()
1077 Elems[i] = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, NTy, in LowerHvxConcatVectors()
1465 if (Op.getOpcode() == ISD::SIGN_EXTEND_INREG) { in SplitHvxPairOp()
1555 case ISD::SIGN_EXTEND_INREG: in LowerHvxOperation()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARC/
DARCISelLowering.cpp138 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Custom); in ARCTargetLowering()
757 case ISD::SIGN_EXTEND_INREG: in LowerOperation()
/external/llvm-project/llvm/lib/Target/ARC/
DARCISelLowering.cpp137 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Custom); in ARCTargetLowering()
758 case ISD::SIGN_EXTEND_INREG: in LowerOperation()
/external/llvm/lib/CodeGen/SelectionDAG/
DLegalizeIntegerTypes.cpp84 case ISD::SIGN_EXTEND_INREG: in PromoteIntegerResult()
461 return DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, NVT, Res, in PromoteIntRes_INT_EXTEND()
556 SDValue Ofl = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, NVT, Res, in PromoteIntRes_SADDSUBO()
640 return DAG.getNode(ISD::SIGN_EXTEND_INREG, SDLoc(N), in PromoteIntRes_SIGN_EXTEND_INREG()
796 SDValue SExt = DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, Mul.getValueType(), in PromoteIntRes_XMULO()
1159 return DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Op.getValueType(), in PromoteIntOp_SIGN_EXTEND()
1329 case ISD::SIGN_EXTEND_INREG: ExpandIntRes_SIGN_EXTEND_INREG(N, Lo, Hi); break; in ExpandIntegerResult()
2448 Hi = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Hi.getValueType(), Hi, in ExpandIntRes_SIGN_EXTEND()
2462 Lo = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Lo.getValueType(), Lo, in ExpandIntRes_SIGN_EXTEND_INREG()
2475 Hi = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Hi.getValueType(), Hi, in ExpandIntRes_SIGN_EXTEND_INREG()
DLegalizeVectorOps.cpp327 case ISD::SIGN_EXTEND_INREG: in LegalizeOp()
679 case ISD::SIGN_EXTEND_INREG: in Expand()
/external/llvm-project/llvm/lib/Target/RISCV/
DRISCVISelDAGToDAG.cpp313 if (N.getOpcode() != ISD::SIGN_EXTEND_INREG || in SelectSLOIW()
/external/llvm-project/llvm/lib/Target/Hexagon/
DHexagonISelLoweringHVX.cpp161 setOperationAction(ISD::SIGN_EXTEND_INREG, T, Custom); in initializeHVXLowering()
237 setOperationAction(ISD::SIGN_EXTEND_INREG, T, Legal); in initializeHVXLowering()
240 setOperationAction(ISD::SIGN_EXTEND_INREG, T, Legal); in initializeHVXLowering()
1265 Elems[i] = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, NTy, in LowerHvxConcatVectors()
1774 if (Op.getOpcode() == ISD::SIGN_EXTEND_INREG) { in SplitHvxPairOp()
2054 case ISD::SIGN_EXTEND_INREG: in LowerHvxOperation()
/external/llvm-project/llvm/lib/Target/Lanai/
DLanaiISelLowering.cpp130 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand); in LanaiTargetLowering()
131 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Expand); in LanaiTargetLowering()
132 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand); in LanaiTargetLowering()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Lanai/
DLanaiISelLowering.cpp130 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand); in LanaiTargetLowering()
131 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Expand); in LanaiTargetLowering()
132 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand); in LanaiTargetLowering()
/external/llvm/lib/Target/Lanai/
DLanaiISelLowering.cpp116 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand); in LanaiTargetLowering()
117 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Expand); in LanaiTargetLowering()
118 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand); in LanaiTargetLowering()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/SelectionDAG/
DLegalizeIntegerTypes.cpp87 case ISD::SIGN_EXTEND_INREG: in PromoteIntegerResult()
578 return DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, NVT, Res, in PromoteIntRes_INT_EXTEND()
867 SDValue Ofl = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, NVT, Res, in PromoteIntRes_SADDSUBO()
954 return DAG.getNode(ISD::SIGN_EXTEND_INREG, SDLoc(N), in PromoteIntRes_SIGN_EXTEND_INREG()
1164 SDValue SExt = DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, Mul.getValueType(), in PromoteIntRes_XMULO()
1563 return DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Op.getValueType(), in PromoteIntOp_SIGN_EXTEND()
1828 case ISD::SIGN_EXTEND_INREG: ExpandIntRes_SIGN_EXTEND_INREG(N, Lo, Hi); break; in ExpandIntegerResult()
3441 Hi = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Hi.getValueType(), Hi, in ExpandIntRes_SIGN_EXTEND()
3455 Lo = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Lo.getValueType(), Lo, in ExpandIntRes_SIGN_EXTEND_INREG()
3467 Hi = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Hi.getValueType(), Hi, in ExpandIntRes_SIGN_EXTEND_INREG()

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