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Searched refs:SI_CONTEXT_INV_L2 (Results 1 – 6 of 6) sorted by relevance

/external/mesa3d/src/gallium/drivers/radeonsi/
Dsi_pipe.h75 #define SI_CONTEXT_INV_L2 (1 << 6) macro
1717 sctx->flags |= SI_CONTEXT_INV_L2; in si_make_CB_shader_coherent()
1726 sctx->flags |= SI_CONTEXT_INV_L2; in si_make_CB_shader_coherent()
1731 sctx->flags |= SI_CONTEXT_INV_L2; in si_make_CB_shader_coherent()
1742 sctx->flags |= SI_CONTEXT_INV_L2; in si_make_DB_shader_coherent()
1751 sctx->flags |= SI_CONTEXT_INV_L2; in si_make_DB_shader_coherent()
1756 sctx->flags |= SI_CONTEXT_INV_L2; in si_make_DB_shader_coherent()
Dsi_state_draw.c1052 SI_CONTEXT_INV_L2 | SI_CONTEXT_WB_L2 | SI_CONTEXT_INV_L2_METADATA | in gfx10_emit_cache_flush()
1090 if (flags & SI_CONTEXT_INV_L2) { in gfx10_emit_cache_flush()
1229 SI_CONTEXT_INV_L2 | SI_CONTEXT_WB_L2 | SI_CONTEXT_INV_L2_METADATA | in si_emit_cache_flush()
1368 if (flags & SI_CONTEXT_INV_L2) { in si_emit_cache_flush()
1373 flags &= ~(SI_CONTEXT_INV_L2 | SI_CONTEXT_WB_L2 | SI_CONTEXT_INV_VCACHE); in si_emit_cache_flush()
1394 SI_CONTEXT_INV_L2 | SI_CONTEXT_WB_L2)))) { in si_emit_cache_flush()
1408 if (flags & SI_CONTEXT_INV_L2 || (sctx->chip_class <= GFX7 && (flags & SI_CONTEXT_WB_L2))) { in si_emit_cache_flush()
Dsi_gfx_cs.c96 wait_flags |= wait_ps_cs | SI_CONTEXT_INV_L2; in si_flush_gfx_cs()
425 SI_CONTEXT_INV_L2 | SI_CONTEXT_START_PIPELINE_STATS; in si_begin_new_gfx_cs()
Dsi_test_dma_perf.c257 (cache_policy == L2_LRU ? 0 : SI_CONTEXT_INV_L2) | in si_test_dma_perf()
Dsi_compute_blit.c55 (cache_policy == L2_BYPASS ? SI_CONTEXT_INV_L2 : 0); in si_get_flush_flags()
Dsi_pipe.c1258 sscreen->barrier_flags.cp_to_L2 |= SI_CONTEXT_INV_L2; in radeonsi_screen_create_impl()