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Searched refs:SI_CONTEXT_REG_OFFSET (Results 1 – 7 of 7) sorted by relevance

/external/mesa3d/src/amd/vulkan/
Dradv_cs.h60 assert(reg >= SI_CONTEXT_REG_OFFSET && reg < SI_CONTEXT_REG_END); in radeon_set_context_reg_seq()
64 radeon_emit(cs, (reg - SI_CONTEXT_REG_OFFSET) >> 2); in radeon_set_context_reg_seq()
78 assert(reg >= SI_CONTEXT_REG_OFFSET && reg < SI_CONTEXT_REG_END); in radeon_set_context_reg_idx()
81 radeon_emit(cs, (reg - SI_CONTEXT_REG_OFFSET) >> 2 | (idx << 28)); in radeon_set_context_reg_idx()
89 assert(reg >= SI_CONTEXT_REG_OFFSET && reg < SI_CONTEXT_REG_END); in radeon_set_context_reg_rmw()
92 radeon_emit(cs, (reg - SI_CONTEXT_REG_OFFSET) >> 2); in radeon_set_context_reg_rmw()
Dradv_cmd_buffer.c2037 radeon_emit(cs, (reg - SI_CONTEXT_REG_OFFSET) >> 2); in radv_load_ds_clear_metadata()
2221 radeon_emit(cs, (reg - SI_CONTEXT_REG_OFFSET) >> 2); in radv_load_color_clear_metadata()
/external/mesa3d/src/gallium/drivers/radeonsi/
Dsi_build_pm4.h45 assert(reg < SI_CONTEXT_REG_OFFSET); in radeon_set_config_reg_seq()
60 assert(reg >= SI_CONTEXT_REG_OFFSET); in radeon_set_context_reg_seq()
63 radeon_emit(cs, (reg - SI_CONTEXT_REG_OFFSET) >> 2); in radeon_set_context_reg_seq()
83 assert(reg >= SI_CONTEXT_REG_OFFSET); in radeon_set_context_reg_idx()
86 radeon_emit(cs, (reg - SI_CONTEXT_REG_OFFSET) >> 2 | (idx << 28)); in radeon_set_context_reg_idx()
140 assert(reg >= SI_CONTEXT_REG_OFFSET); in radeon_set_context_reg_rmw()
143 radeon_emit(cs, (reg - SI_CONTEXT_REG_OFFSET) >> 2); in radeon_set_context_reg_rmw()
Dsi_pm4.c65 } else if (reg >= SI_CONTEXT_REG_OFFSET && reg < SI_CONTEXT_REG_END) { in si_pm4_set_reg()
67 reg -= SI_CONTEXT_REG_OFFSET; in si_pm4_set_reg()
Dsi_cp_reg_shadowing.c49 offset = SI_CONTEXT_REG_OFFSET; in si_build_load_reg()
/external/mesa3d/src/amd/common/
Dsid.h34 #define SI_CONTEXT_REG_OFFSET 0x00028000 macro
43 #define SI_CONTEXT_REG_SPACE_SIZE (SI_CONTEXT_REG_END - SI_CONTEXT_REG_OFFSET)
Dac_debug.c266 ac_parse_set_reg_packet(f, count, SI_CONTEXT_REG_OFFSET, ib); in ac_parse_packet3()