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Searched refs:SI_SH_REG_OFFSET (Results 1 – 12 of 12) sorted by relevance

/external/mesa3d/src/amd/vulkan/
Dradv_cs.h99 assert(reg >= SI_SH_REG_OFFSET && reg < SI_SH_REG_END); in radeon_set_sh_reg_seq()
103 radeon_emit(cs, (reg - SI_SH_REG_OFFSET) >> 2); in radeon_set_sh_reg_seq()
117 assert(reg >= SI_SH_REG_OFFSET && reg < SI_SH_REG_END); in radeon_set_sh_reg_idx()
126 radeon_emit(cs, (reg - SI_SH_REG_OFFSET) >> 2 | (idx << 28)); in radeon_set_sh_reg_idx()
Dradv_cmd_buffer.c5108 radeon_emit(cs, (base_reg - SI_SH_REG_OFFSET) >> 2); in radv_cs_emit_indirect_draw_packet()
5109 radeon_emit(cs, ((base_reg + 4) - SI_SH_REG_OFFSET) >> 2); in radv_cs_emit_indirect_draw_packet()
5116 radeon_emit(cs, (base_reg - SI_SH_REG_OFFSET) >> 2); in radv_cs_emit_indirect_draw_packet()
5117 radeon_emit(cs, ((base_reg + 4) - SI_SH_REG_OFFSET) >> 2); in radv_cs_emit_indirect_draw_packet()
5118 radeon_emit(cs, (((base_reg + 8) - SI_SH_REG_OFFSET) >> 2) | in radv_cs_emit_indirect_draw_packet()
Dradv_private.h1590 radeon_emit(cs, (sh_offset - SI_SH_REG_OFFSET) >> 2); in radv_emit_shader_pointer_head()
/external/mesa3d/src/gallium/drivers/radeonsi/
Dsi_pm4.c61 } else if (reg >= SI_SH_REG_OFFSET && reg < SI_SH_REG_END) { in si_pm4_set_reg()
63 reg -= SI_SH_REG_OFFSET; in si_pm4_set_reg()
Dsi_build_pm4.h93 assert(reg >= SI_SH_REG_OFFSET && reg < SI_SH_REG_END); in radeon_set_sh_reg_seq()
96 radeon_emit(cs, (reg - SI_SH_REG_OFFSET) >> 2); in radeon_set_sh_reg_seq()
Dsi_cp_reg_shadowing.c54 offset = SI_SH_REG_OFFSET; in si_build_load_reg()
Dsi_state_draw.c875 radeon_emit(cs, (sh_base_reg + SI_SGPR_BASE_VERTEX * 4 - SI_SH_REG_OFFSET) >> 2); in si_emit_draw_packets()
876 radeon_emit(cs, (sh_base_reg + SI_SGPR_START_INSTANCE * 4 - SI_SH_REG_OFFSET) >> 2); in si_emit_draw_packets()
894 radeon_emit(cs, (sh_base_reg + SI_SGPR_BASE_VERTEX * 4 - SI_SH_REG_OFFSET) >> 2); in si_emit_draw_packets()
895 radeon_emit(cs, (sh_base_reg + SI_SGPR_START_INSTANCE * 4 - SI_SH_REG_OFFSET) >> 2); in si_emit_draw_packets()
896 radeon_emit(cs, ((sh_base_reg + SI_SGPR_DRAWID * 4 - SI_SH_REG_OFFSET) >> 2) | in si_emit_draw_packets()
Dsi_descriptors.c1962 radeon_emit(cs, (sh_offset - SI_SH_REG_OFFSET) >> 2); in si_emit_shader_pointer_head()
/external/mesa3d/src/gallium/drivers/r600/
Dr600_cs.h172 assert(reg >= SI_SH_REG_OFFSET && reg < SI_SH_REG_END); in radeon_set_sh_reg_seq()
175 radeon_emit(cs, (reg - SI_SH_REG_OFFSET) >> 2); in radeon_set_sh_reg_seq()
Dr600d_common.h31 #define SI_SH_REG_OFFSET 0x0000B000 macro
/external/mesa3d/src/amd/common/
Dsid.h32 #define SI_SH_REG_OFFSET 0x0000B000 macro
42 #define SI_SH_REG_SPACE_SIZE (SI_SH_REG_END - SI_SH_REG_OFFSET)
Dac_debug.c276 ac_parse_set_reg_packet(f, count, SI_SH_REG_OFFSET, ib); in ac_parse_packet3()