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Searched refs:SLT (Results 1 – 25 of 75) sorted by relevance

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/external/llvm/lib/Target/AMDGPU/
DAMDGPUTargetTransformInfo.cpp130 MVT::SimpleValueType SLT = LT.second.getScalarType().SimpleTy; in getArithmeticInstrCost() local
136 if (SLT == MVT::i64) in getArithmeticInstrCost()
147 if (SLT == MVT::i64){ in getArithmeticInstrCost()
156 if (SLT == MVT::i64) { in getArithmeticInstrCost()
167 if (SLT == MVT::f64) in getArithmeticInstrCost()
170 if (SLT == MVT::f32 || SLT == MVT::f16) in getArithmeticInstrCost()
178 if (SLT == MVT::f64) { in getArithmeticInstrCost()
189 if (SLT == MVT::f32 || SLT == MVT::f16) { in getArithmeticInstrCost()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/
DAMDGPUTargetTransformInfo.cpp363 MVT::SimpleValueType SLT = LT.second.getScalarType().SimpleTy; in getArithmeticInstrCost() local
369 if (SLT == MVT::i64) in getArithmeticInstrCost()
372 if (ST->has16BitInsts() && SLT == MVT::i16) in getArithmeticInstrCost()
382 if (SLT == MVT::i64) { in getArithmeticInstrCost()
387 if (ST->has16BitInsts() && SLT == MVT::i16) in getArithmeticInstrCost()
393 if (SLT == MVT::i64) { in getArithmeticInstrCost()
398 if (ST->has16BitInsts() && SLT == MVT::i16) in getArithmeticInstrCost()
407 if (SLT == MVT::f64) in getArithmeticInstrCost()
410 if (ST->has16BitInsts() && SLT == MVT::f16) in getArithmeticInstrCost()
413 if (SLT == MVT::f32 || SLT == MVT::f16) in getArithmeticInstrCost()
[all …]
/external/llvm-project/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/
Dicmp.mir85 ; MIPS32: [[SLT:%[0-9]+]]:gpr32 = SLT [[COPY1]], [[COPY]]
86 ; MIPS32: $v0 = COPY [[SLT]]
110 ; MIPS32: [[SLT:%[0-9]+]]:gpr32 = SLT [[COPY]], [[COPY1]]
111 ; MIPS32: [[XORi:%[0-9]+]]:gpr32 = XORi [[SLT]], 1
136 ; MIPS32: [[SLT:%[0-9]+]]:gpr32 = SLT [[COPY]], [[COPY1]]
137 ; MIPS32: $v0 = COPY [[SLT]]
161 ; MIPS32: [[SLT:%[0-9]+]]:gpr32 = SLT [[COPY1]], [[COPY]]
162 ; MIPS32: [[XORi:%[0-9]+]]:gpr32 = XORi [[SLT]], 1
/external/llvm-project/llvm/lib/Target/AMDGPU/
DAMDGPUTargetTransformInfo.cpp530 MVT::SimpleValueType SLT = LT.second.getScalarType().SimpleTy; in getArithmeticInstrCost() local
536 if (SLT == MVT::i64) in getArithmeticInstrCost()
539 if (ST->has16BitInsts() && SLT == MVT::i16) in getArithmeticInstrCost()
549 if (SLT == MVT::i64) { in getArithmeticInstrCost()
554 if (ST->has16BitInsts() && SLT == MVT::i16) in getArithmeticInstrCost()
560 if (SLT == MVT::i64) { in getArithmeticInstrCost()
565 if (ST->has16BitInsts() && SLT == MVT::i16) in getArithmeticInstrCost()
579 if (ST->hasMadMacF32Insts() && SLT == MVT::f32 && !HasFP32Denormals) in getArithmeticInstrCost()
581 if (ST->has16BitInsts() && SLT == MVT::f16 && !HasFP64FP16Denormals) in getArithmeticInstrCost()
595 if (SLT == MVT::f64) in getArithmeticInstrCost()
[all …]
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/
DMipsExpandPseudo.cpp311 unsigned LL, SC, SLT, SLTu, OR, MOVN, MOVZ, SELNEZ, SELEQZ; in expandAtomicBinOpSubword() local
319 SLT = Mips::SLT_MM; in expandAtomicBinOpSubword()
331 SLT = Mips::SLT; in expandAtomicBinOpSubword()
457 unsigned SLTScratch4 = IsUnsigned ? SLTu : SLT; in expandAtomicBinOpSubword()
586 unsigned LL, SC, ZERO, BEQ, SLT, SLTu, OR, MOVN, MOVZ, SELNEZ, SELEQZ; in expandAtomicBinOp() local
593 SLT = Mips::SLT_MM; in expandAtomicBinOp()
608 SLT = Mips::SLT; in expandAtomicBinOp()
623 SLT = Mips::SLT64; in expandAtomicBinOp()
743 unsigned SLTScratch2 = IsUnsigned ? SLTu : SLT; in expandAtomicBinOp()
DMipsCondMov.td199 defm : MovzPats0<GPR32, GPR32, MOVZ_I_I, SLT, SLTu, SLTi, SLTiu>,
204 defm : MovzPats0<GPR32, GPR64, MOVZ_I_I64, SLT, SLTu, SLTi, SLTiu>,
232 defm : MovzPats0<GPR32, FGR32, MOVZ_I_S, SLT, SLTu, SLTi, SLTiu>,
244 defm : MovzPats0<GPR32, AFGR64, MOVZ_I_D32, SLT, SLTu, SLTi, SLTiu>,
251 defm : MovzPats0<GPR32, FGR64, MOVZ_I_D64, SLT, SLTu, SLTi, SLTiu>,
DMipsInstructionSelector.cpp688 Instructions.emplace_back(Mips::SLT, ICMPReg, RHS, LHS); in select()
691 Instructions.emplace_back(Mips::SLT, Temp, LHS, RHS); in select()
695 Instructions.emplace_back(Mips::SLT, ICMPReg, LHS, RHS); in select()
698 Instructions.emplace_back(Mips::SLT, Temp, RHS, LHS); in select()
/external/llvm-project/llvm/lib/Target/Mips/
DMipsExpandPseudo.cpp311 unsigned LL, SC, SLT, SLTu, OR, MOVN, MOVZ, SELNEZ, SELEQZ; in expandAtomicBinOpSubword() local
319 SLT = Mips::SLT_MM; in expandAtomicBinOpSubword()
331 SLT = Mips::SLT; in expandAtomicBinOpSubword()
457 unsigned SLTScratch4 = IsUnsigned ? SLTu : SLT; in expandAtomicBinOpSubword()
586 unsigned LL, SC, ZERO, BEQ, SLT, SLTu, OR, MOVN, MOVZ, SELNEZ, SELEQZ; in expandAtomicBinOp() local
593 SLT = Mips::SLT_MM; in expandAtomicBinOp()
608 SLT = Mips::SLT; in expandAtomicBinOp()
623 SLT = Mips::SLT64; in expandAtomicBinOp()
743 unsigned SLTScratch2 = IsUnsigned ? SLTu : SLT; in expandAtomicBinOp()
DMipsCondMov.td199 defm : MovzPats0<GPR32, GPR32, MOVZ_I_I, SLT, SLTu, SLTi, SLTiu>,
204 defm : MovzPats0<GPR32, GPR64, MOVZ_I_I64, SLT, SLTu, SLTi, SLTiu>,
232 defm : MovzPats0<GPR32, FGR32, MOVZ_I_S, SLT, SLTu, SLTi, SLTiu>,
244 defm : MovzPats0<GPR32, AFGR64, MOVZ_I_D32, SLT, SLTu, SLTi, SLTiu>,
251 defm : MovzPats0<GPR32, FGR64, MOVZ_I_D64, SLT, SLTu, SLTi, SLTiu>,
DMipsInstructionSelector.cpp787 Instructions.emplace_back(Mips::SLT, ICMPReg, RHS, LHS); in select()
790 Instructions.emplace_back(Mips::SLT, Temp, LHS, RHS); in select()
794 Instructions.emplace_back(Mips::SLT, ICMPReg, LHS, RHS); in select()
797 Instructions.emplace_back(Mips::SLT, Temp, RHS, LHS); in select()
/external/llvm-project/llvm/test/CodeGen/Hexagon/loop-idiom/
Dmemmove-rt-check.ll11 ; CHECK: [[SLT:%[0-9]+]] = icmp sle i32 [[LEN]], [[SUB]]
12 ; CHECK: [[CND:%[0-9]+]] = or i1 [[ULT]], [[SLT]]
/external/mesa3d/src/gallium/tests/graw/fragment-shader/
Dfrag-slt.sh10 SLT TEMP[0], IN[0], IMM[0]
Dfrag-kil.sh12 SLT TEMP[0], IN[0], IMM[0]
/external/mesa3d/src/gallium/tests/graw/vertex-shader/
Dvert-slt.sh12 SLT TEMP[0], IN[0], IMM[0]
/external/llvm/lib/Target/Mips/
DMipsCondMov.td199 defm : MovzPats0<GPR32, GPR32, MOVZ_I_I, SLT, SLTu, SLTi, SLTiu>,
204 defm : MovzPats0<GPR32, GPR64, MOVZ_I_I64, SLT, SLTu, SLTi, SLTiu>,
232 defm : MovzPats0<GPR32, FGR32, MOVZ_I_S, SLT, SLTu, SLTi, SLTiu>,
244 defm : MovzPats0<GPR32, AFGR64, MOVZ_I_D32, SLT, SLTu, SLTi, SLTiu>,
251 defm : MovzPats0<GPR32, FGR64, MOVZ_I_D64, SLT, SLTu, SLTi, SLTiu>,
/external/llvm-project/polly/test/ScopInfo/
Dcfg_consequences.ll15 ; SLT: *A = 0;
247 br label %SLT
249 SLT: ; preds = %if.end.3
258 M_SLT: ; preds = %S_SLT, %SLT
/external/llvm-project/llvm/test/MC/Mips/
Dinstalias-imm-expanding.s566 # MIPS-NEXT: # <MCInst #{{[0-9]+}} SLT
574 # MIPS-NEXT: # <MCInst #{{[0-9]+}} SLT
592 # MIPS-NEXT: # <MCInst #{{[0-9]+}} SLT
600 # MIPS-NEXT: # <MCInst #{{[0-9]+}} SLT
606 # MIPS-NEXT: # <MCInst #{{[0-9]+}} SLT
613 # MIPS-NEXT: # <MCInst #{{[0-9]+}} SLT
/external/mesa3d/docs/relnotes/
D9.2.4.rst71 - freedreno/a3xx/compiler: fix SGT/SLT/etc
/external/virglrenderer/src/gallium/auxiliary/tgsi/
Dtgsi_opcode_tmp.h73 OP12(SLT)
/external/mesa3d/src/gallium/auxiliary/tgsi/
Dtgsi_opcode_tmp.h56 OP12(SLT)
/external/mesa3d/src/mesa/program/
Dprogram_lexer.l227 SLT{sat} { return_opcode( 1, BIN_OP, SLT, 3); }
/external/capstone/arch/EVM/
DEVMMappingInsn.inc22 { 2, 1, 3 }, // SLT
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/RISCV/
DRISCVInstrInfo.td429 def SLT : ALU_rr<0b0000000, 0b010, "slt">, Sched<[WriteIALU, ReadIALU, ReadIALU]>;
601 def : InstAlias<"sltz $rd, $rs", (SLT GPR:$rd, GPR:$rs, X0)>;
602 def : InstAlias<"sgtz $rd, $rs", (SLT GPR:$rd, X0, GPR:$rs)>;
606 def : InstAlias<"sgt $rd, $rs, $rt", (SLT GPR:$rd, GPR:$rt, GPR:$rs), 0>;
839 def : PatGprGpr<setlt, SLT>;
857 def : Pat<(setgt GPR:$rs1, GPR:$rs2), (SLT GPR:$rs2, GPR:$rs1)>;
858 def : Pat<(setge GPR:$rs1, GPR:$rs2), (XORI (SLT GPR:$rs1, GPR:$rs2), 1)>;
859 def : Pat<(setle GPR:$rs1, GPR:$rs2), (XORI (SLT GPR:$rs2, GPR:$rs1), 1)>;
/external/llvm-project/llvm/lib/Target/RISCV/
DRISCVInstrInfo.td479 def SLT : ALU_rr<0b0000000, 0b010, "slt">, Sched<[WriteIALU, ReadIALU, ReadIALU]>;
663 def : InstAlias<"sltz $rd, $rs", (SLT GPR:$rd, GPR:$rs, X0)>;
664 def : InstAlias<"sgtz $rd, $rs", (SLT GPR:$rd, X0, GPR:$rs)>;
668 def : InstAlias<"sgt $rd, $rs, $rt", (SLT GPR:$rd, GPR:$rt, GPR:$rs), 0>;
901 def : PatGprGpr<setlt, SLT>;
919 def : Pat<(setgt GPR:$rs1, GPR:$rs2), (SLT GPR:$rs2, GPR:$rs1)>;
920 def : Pat<(setge GPR:$rs1, GPR:$rs2), (XORI (SLT GPR:$rs1, GPR:$rs2), 1)>;
921 def : Pat<(setle GPR:$rs1, GPR:$rs2), (XORI (SLT GPR:$rs2, GPR:$rs1), 1)>;
/external/llvm-project/llvm/test/CodeGen/SystemZ/
Dbranch-07.ll52 ; Test SLT.

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