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Searched refs:SOC15_REG_ADDR (Results 1 – 2 of 2) sorted by relevance

/external/mesa3d/src/gallium/drivers/radeon/
Dradeon_vcn_dec_jpeg.c71 set_reg_jpeg(dec, SOC15_REG_ADDR(mmUVD_JPEG_CNTL), COND0, TYPE0, 1); in send_cmd_bitstream()
74 set_reg_jpeg(dec, SOC15_REG_ADDR(mmUVD_CTX_INDEX), COND0, TYPE0, 0x01C2); in send_cmd_bitstream()
75 set_reg_jpeg(dec, SOC15_REG_ADDR(mmUVD_CTX_DATA), COND0, TYPE0, 0x01400200); in send_cmd_bitstream()
76 set_reg_jpeg(dec, SOC15_REG_ADDR(mmUVD_CTX_INDEX), COND0, TYPE0, 0x01C3); in send_cmd_bitstream()
77 set_reg_jpeg(dec, SOC15_REG_ADDR(mmUVD_CTX_DATA), COND0, TYPE0, (1 << 9)); in send_cmd_bitstream()
78 set_reg_jpeg(dec, SOC15_REG_ADDR(mmUVD_SOFT_RESET), COND0, TYPE3, (1 << 9)); in send_cmd_bitstream()
81 set_reg_jpeg(dec, SOC15_REG_ADDR(mmUVD_JPEG_CNTL), COND0, TYPE0, 0); in send_cmd_bitstream()
84 set_reg_jpeg(dec, SOC15_REG_ADDR(mmUVD_CTX_INDEX), COND0, TYPE0, 0x01C3); in send_cmd_bitstream()
85 set_reg_jpeg(dec, SOC15_REG_ADDR(mmUVD_CTX_DATA), COND0, TYPE0, (0 << 9)); in send_cmd_bitstream()
86 set_reg_jpeg(dec, SOC15_REG_ADDR(mmUVD_SOFT_RESET), COND0, TYPE3, (1 << 9)); in send_cmd_bitstream()
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Dradeon_vcn_dec.h202 #define SOC15_REG_ADDR(reg) (UVD_BASE_INST0_SEG1 + reg) macro