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Searched refs:SOP1 (Results 1 – 25 of 28) sorted by relevance

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/external/llvm/docs/
DAMDGPUUsage.rst63 SOP1 Instructions
65 All SOP1 instructions are supported.
/external/mesa3d/src/amd/compiler/
Daco_opcodes.py35 SOP1 = 1 variable in Format
391 SOP1 = { variable
464 for (gfx6, gfx7, gfx8, gfx9, gfx10, name) in SOP1:
465 opcode(name, gfx7, gfx9, gfx10, Format.SOP1)
Daco_validate.cpp237 check(instr->format == Format::SOP1 || in validate_ir()
319 if (instr->format == Format::SOP1 || instr->format == Format::SOP2) { in validate_ir()
Daco_ir.h72 SOP1 = 1, enumerator
928 return format == Format::SOP1 || in isSALU()
Daco_spill.cpp246 …if (instr->format != Format::VOP1 && instr->format != Format::SOP1 && instr->format != Format::PSE… in should_rematerialize()
273 …assert((instr->format == Format::VOP1 || instr->format == Format::SOP1 || instr->format == Format:… in do_reload()
280 } else if (instr->format == Format::SOP1) { in do_reload()
Daco_insert_NOPs.cpp689 …nstruction> s_mov{create_instruction<SOP1_instruction>(aco_opcode::s_mov_b32, Format::SOP1, 1, 1)}; in handle_instruction_gfx10()
Daco_assembler.cpp139 case Format::SOP1: { in emit_instruction()
Daco_insert_exec_mask.cpp760 …instr.reset(create_instruction<SOP1_instruction>(bld.w64or32(Builder::s_mov), Format::SOP1, 1, 1)); in process_instructions()
Daco_register_allocation.cpp2365 … mov.reset(create_instruction<SOP1_instruction>(aco_opcode::s_mov_b32, Format::SOP1, 1, 1)); in register_allocation()
/external/llvm/lib/Target/AMDGPU/
DSIInstrFormats.td25 field bits<1> SOP1 = 0;
61 let TSFlags{5} = SOP1;
282 class SOP1 <dag outs, dag ins, string asm, list<dag> pattern> :
289 let SOP1 = 1;
DSIDefines.h22 SOP1 = 1 << 5, enumerator
DSIInstrInfo.h208 return MI.getDesc().TSFlags & SIInstrFlags::SOP1; in isSOP1()
212 return get(Opcode).TSFlags & SIInstrFlags::SOP1; in isSOP1()
DSIInstrInfo.td718 SOP1 <outs, ins, "", pattern>,
725 SOP1 <outs, ins, asm, []>,
735 SOP1 <outs, ins, asm, []>,
DSIInstructions.td87 // SOP1 Instructions
2421 // SOP1 Patterns
/external/llvm-project/llvm/lib/Target/AMDGPU/
DSIInstrFormats.td21 field bit SOP1 = 0;
142 let TSFlags{2} = SOP1;
DSOPInstructions.td37 // SOP1 Instructions
48 let SOP1 = 1;
1324 // SOP1 Patterns
1432 // SOP1 - GFX10.
1460 // SOP1 - GFX6, GFX7.
1958 // SOP1 - GFX9.
DSIDefines.h25 SOP1 = 1 << 2, enumerator
DSIInstrInfo.h364 return MI.getDesc().TSFlags & SIInstrFlags::SOP1; in isSOP1()
368 return get(Opcode).TSFlags & SIInstrFlags::SOP1; in isSOP1()
DSIInstructions.td569 let SOP1 = 1;
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/
DSIInstrFormats.td21 field bit SOP1 = 0;
134 let TSFlags{2} = SOP1;
DSIDefines.h25 SOP1 = 1 << 2, enumerator
DSOPInstructions.td37 // SOP1 Instructions
48 let SOP1 = 1;
1199 // SOP1 Patterns
1269 // SOP1 - GFX10.
1302 // SOP1 - GFX6, GFX7.
1660 // SOP1 - GFX9.
DSIInstrInfo.h358 return MI.getDesc().TSFlags & SIInstrFlags::SOP1; in isSOP1()
362 return get(Opcode).TSFlags & SIInstrFlags::SOP1; in isSOP1()
/external/llvm-project/llvm/docs/AMDGPU/
DAMDGPUAsmGFX7.rst442 SOP1 section in Instructions
/external/llvm-project/llvm/docs/
DAMDGPUUsage.rst8790 SOP1 subsubsection
8803 For full list of supported instructions, refer to "SOP1 Instructions" in ISA

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