| /external/llvm-project/llvm/test/CodeGen/AMDGPU/ |
| D | verify-sop.mir | 3 # CHECK: *** Bad machine code: SOP2/SOPC instruction requires too many immediate constants
6 # CHECK: *** Bad machine code: SOP2/SOPC instruction requires too many immediate constants
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| /external/llvm/docs/ |
| D | AMDGPUUsage.rst | 67 SOP2 Instructions
69 All SOP2 instructions are supported.
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| /external/mesa3d/src/amd/compiler/ |
| D | aco_opcodes.py | 36 SOP2 = 2 variable in Format
294 SOP2 = { variable
350 for (gfx6, gfx7, gfx8, gfx9, gfx10, name) in SOP2:
351 opcode(name, gfx7, gfx9, gfx10, Format.SOP2)
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| D | aco_validate.cpp | 238 instr->format == Format::SOP2 || in validate_ir()
319 if (instr->format == Format::SOP1 || instr->format == Format::SOP2) { in validate_ir()
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| D | aco_ir.h | 73 SOP2 = 2, enumerator
929 format == Format::SOP2 || in isSALU()
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| D | aco_assembler.cpp | 102 case Format::SOP2: { in emit_instruction()
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| D | aco_insert_exec_mask.cpp | 780 …str.reset(create_instruction<SOP2_instruction>(bld.w64or32(Builder::s_andn2), Format::SOP2, 2, 2)); in process_instructions()
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| /external/llvm/lib/Target/AMDGPU/ |
| D | SIInstrFormats.td | 26 field bits<1> SOP2 = 0;
62 let TSFlags{6} = SOP2;
292 class SOP2 <dag outs, dag ins, string asm, list<dag> pattern> :
300 let SOP2 = 1;
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| D | SIDefines.h | 23 SOP2 = 1 << 6, enumerator
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| D | SIInstrInfo.h | 216 return MI.getDesc().TSFlags & SIInstrFlags::SOP2; in isSOP2()
220 return get(Opcode).TSFlags & SIInstrFlags::SOP2; in isSOP2()
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| D | SIInstrInfo.td | 808 SOP2<outs, ins, "", pattern>,
822 SOP2<outs, ins, asm, []>,
831 SOP2<outs, ins, asm, []>,
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| D | SIInstructions.td | 192 // SOP2 Instructions
2437 // SOP2 Patterns
|
| /external/llvm-project/llvm/lib/Target/AMDGPU/ |
| D | SIInstrFormats.td | 22 field bit SOP2 = 0;
143 let TSFlags{3} = SOP2;
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| D | SOPInstructions.td | 337 // SOP2 Instructions
348 let SOP2 = 1;
1362 // SOP2 Patterns
1523 // SOP2 - GFX10.
1542 // SOP2 - GFX6, GFX7.
1968 // SOP2 - GFX9.
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| D | SIDefines.h | 26 SOP2 = 1 << 3, enumerator
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| D | SIInstrInfo.h | 372 return MI.getDesc().TSFlags & SIInstrFlags::SOP2; in isSOP2()
376 return get(Opcode).TSFlags & SIInstrFlags::SOP2; in isSOP2()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
| D | SIInstrFormats.td | 22 field bit SOP2 = 0;
135 let TSFlags{3} = SOP2;
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| D | SIDefines.h | 26 SOP2 = 1 << 3, enumerator
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| D | SOPInstructions.td | 324 // SOP2 Instructions
335 let SOP2 = 1;
1232 // SOP2 Patterns
1371 // SOP2 - GFX10.
1390 // SOP2 - GFX6, GFX7.
1670 // SOP2 - GFX9.
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| D | SIInstrInfo.h | 366 return MI.getDesc().TSFlags & SIInstrFlags::SOP2; in isSOP2()
370 return get(Opcode).TSFlags & SIInstrFlags::SOP2; in isSOP2()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/AsmParser/ |
| D | AMDGPUAsmParser.cpp | 3341 if (!(Desc.TSFlags & (SIInstrFlags::SOP2 | SIInstrFlags::SOPC))) in validateSOPLiteral()
|
| /external/llvm-project/llvm/lib/Target/AMDGPU/AsmParser/ |
| D | AMDGPUAsmParser.cpp | 3716 if (!(Desc.TSFlags & (SIInstrFlags::SOP2 | SIInstrFlags::SOPC))) in validateSOPLiteral()
|
| /external/llvm-project/llvm/docs/AMDGPU/ |
| D | AMDGPUAsmGFX7.rst | 498 SOP2 section in Instructions
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| D | AMDGPUAsmGFX8.rst | 520 SOP2 section in Instructions
|
| /external/llvm-project/llvm/docs/ |
| D | AMDGPUUsage.rst | 8806 SOP2 subsubsection
8821 For full list of supported instructions, refer to "SOP2 Instructions" in ISA
|