| /external/llvm/lib/Target/Sparc/Disassembler/ |
| D | SparcDisassembler.cpp | 68 SP::G0, SP::G1, SP::G2, SP::G3,
69 SP::G4, SP::G5, SP::G6, SP::G7,
70 SP::O0, SP::O1, SP::O2, SP::O3,
71 SP::O4, SP::O5, SP::O6, SP::O7,
72 SP::L0, SP::L1, SP::L2, SP::L3,
73 SP::L4, SP::L5, SP::L6, SP::L7,
74 SP::I0, SP::I1, SP::I2, SP::I3,
75 SP::I4, SP::I5, SP::I6, SP::I7 };
78 SP::F0, SP::F1, SP::F2, SP::F3,
79 SP::F4, SP::F5, SP::F6, SP::F7,
[all …]
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Sparc/Disassembler/ |
| D | SparcDisassembler.cpp | 61 SP::G0, SP::G1, SP::G2, SP::G3,
62 SP::G4, SP::G5, SP::G6, SP::G7,
63 SP::O0, SP::O1, SP::O2, SP::O3,
64 SP::O4, SP::O5, SP::O6, SP::O7,
65 SP::L0, SP::L1, SP::L2, SP::L3,
66 SP::L4, SP::L5, SP::L6, SP::L7,
67 SP::I0, SP::I1, SP::I2, SP::I3,
68 SP::I4, SP::I5, SP::I6, SP::I7 };
71 SP::F0, SP::F1, SP::F2, SP::F3,
72 SP::F4, SP::F5, SP::F6, SP::F7,
[all …]
|
| /external/llvm-project/llvm/lib/Target/Sparc/Disassembler/ |
| D | SparcDisassembler.cpp | 61 SP::G0, SP::G1, SP::G2, SP::G3,
62 SP::G4, SP::G5, SP::G6, SP::G7,
63 SP::O0, SP::O1, SP::O2, SP::O3,
64 SP::O4, SP::O5, SP::O6, SP::O7,
65 SP::L0, SP::L1, SP::L2, SP::L3,
66 SP::L4, SP::L5, SP::L6, SP::L7,
67 SP::I0, SP::I1, SP::I2, SP::I3,
68 SP::I4, SP::I5, SP::I6, SP::I7 };
71 SP::F0, SP::F1, SP::F2, SP::F3,
72 SP::F4, SP::F5, SP::F6, SP::F7,
[all …]
|
| /external/llvm-project/compiler-rt/lib/xray/ |
| D | xray_trampoline_AArch64.S | 22 STP X1, X2, [SP, #-16]!
23 STP X3, X4, [SP, #-16]!
24 STP X5, X6, [SP, #-16]!
25 STP X7, X30, [SP, #-16]!
26 STP Q0, Q1, [SP, #-32]!
27 STP Q2, Q3, [SP, #-32]!
28 STP Q4, Q5, [SP, #-32]!
29 STP Q6, Q7, [SP, #-32]!
32 STP X8, X0, [SP, #-16]!
48 LDP X8, X0, [SP], #16
[all …]
|
| /external/llvm/lib/Target/Sparc/InstPrinter/ |
| D | SparcInstPrinter.cpp | 30 using namespace SP;
59 case SP::JMPLrr: in printSparcAliasInstr()
60 case SP::JMPLri: { in printSparcAliasInstr()
67 case SP::G0: // jmp $addr | ret | retl in printSparcAliasInstr()
72 case SP::I7: O << "\tret"; return true; in printSparcAliasInstr()
73 case SP::O7: O << "\tretl"; return true; in printSparcAliasInstr()
78 case SP::O7: // call $addr in printSparcAliasInstr()
83 case SP::V9FCMPS: case SP::V9FCMPD: case SP::V9FCMPQ: in printSparcAliasInstr()
84 case SP::V9FCMPES: case SP::V9FCMPED: case SP::V9FCMPEQ: { in printSparcAliasInstr()
88 || (MI->getOperand(0).getReg() != SP::FCC0)) in printSparcAliasInstr()
[all …]
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Sparc/MCTargetDesc/ |
| D | SparcInstPrinter.cpp | 29 using namespace SP;
59 case SP::JMPLrr: in printSparcAliasInstr()
60 case SP::JMPLri: { in printSparcAliasInstr()
67 case SP::G0: // jmp $addr | ret | retl in printSparcAliasInstr()
72 case SP::I7: O << "\tret"; return true; in printSparcAliasInstr()
73 case SP::O7: O << "\tretl"; return true; in printSparcAliasInstr()
78 case SP::O7: // call $addr in printSparcAliasInstr()
83 case SP::V9FCMPS: case SP::V9FCMPD: case SP::V9FCMPQ: in printSparcAliasInstr()
84 case SP::V9FCMPES: case SP::V9FCMPED: case SP::V9FCMPEQ: { in printSparcAliasInstr()
88 || (MI->getOperand(0).getReg() != SP::FCC0)) in printSparcAliasInstr()
[all …]
|
| /external/llvm-project/llvm/lib/Target/Sparc/MCTargetDesc/ |
| D | SparcInstPrinter.cpp | 29 using namespace SP;
60 case SP::JMPLrr: in printSparcAliasInstr()
61 case SP::JMPLri: { in printSparcAliasInstr()
68 case SP::G0: // jmp $addr | ret | retl in printSparcAliasInstr()
73 case SP::I7: O << "\tret"; return true; in printSparcAliasInstr()
74 case SP::O7: O << "\tretl"; return true; in printSparcAliasInstr()
79 case SP::O7: // call $addr in printSparcAliasInstr()
84 case SP::V9FCMPS: case SP::V9FCMPD: case SP::V9FCMPQ: in printSparcAliasInstr()
85 case SP::V9FCMPES: case SP::V9FCMPED: case SP::V9FCMPEQ: { in printSparcAliasInstr()
89 || (MI->getOperand(0).getReg() != SP::FCC0)) in printSparcAliasInstr()
[all …]
|
| /external/llvm/lib/Target/Sparc/ |
| D | SparcFrameLowering.cpp | 52 BuildMI(MBB, MBBI, dl, TII.get(ADDri), SP::O6) in emitSPAdjustment()
53 .addReg(SP::O6).addImm(NumBytes); in emitSPAdjustment()
64 BuildMI(MBB, MBBI, dl, TII.get(SP::SETHIi), SP::G1) in emitSPAdjustment()
66 BuildMI(MBB, MBBI, dl, TII.get(SP::ORri), SP::G1) in emitSPAdjustment()
67 .addReg(SP::G1).addImm(LO10(NumBytes)); in emitSPAdjustment()
68 BuildMI(MBB, MBBI, dl, TII.get(ADDrr), SP::O6) in emitSPAdjustment()
69 .addReg(SP::O6).addReg(SP::G1); in emitSPAdjustment()
77 BuildMI(MBB, MBBI, dl, TII.get(SP::SETHIi), SP::G1) in emitSPAdjustment()
79 BuildMI(MBB, MBBI, dl, TII.get(SP::XORri), SP::G1) in emitSPAdjustment()
80 .addReg(SP::G1).addImm(LOX10(NumBytes)); in emitSPAdjustment()
[all …]
|
| D | SparcRegisterInfo.cpp | 37 SparcRegisterInfo::SparcRegisterInfo() : SparcGenRegisterInfo(SP::O7) {} in SparcRegisterInfo()
59 Reserved.set(SP::G1); in getReservedRegs()
63 Reserved.set(SP::G2); in getReservedRegs()
64 Reserved.set(SP::G3); in getReservedRegs()
65 Reserved.set(SP::G4); in getReservedRegs()
69 Reserved.set(SP::G5); in getReservedRegs()
71 Reserved.set(SP::O6); in getReservedRegs()
72 Reserved.set(SP::I6); in getReservedRegs()
73 Reserved.set(SP::I7); in getReservedRegs()
74 Reserved.set(SP::G0); in getReservedRegs()
[all …]
|
| D | SparcInstrInfo.cpp | 36 : SparcGenInstrInfo(SP::ADJCALLSTACKDOWN, SP::ADJCALLSTACKUP), RI(), in SparcInstrInfo()
46 if (MI.getOpcode() == SP::LDri || MI.getOpcode() == SP::LDXri || in isLoadFromStackSlot()
47 MI.getOpcode() == SP::LDFri || MI.getOpcode() == SP::LDDFri || in isLoadFromStackSlot()
48 MI.getOpcode() == SP::LDQFri) { in isLoadFromStackSlot()
65 if (MI.getOpcode() == SP::STri || MI.getOpcode() == SP::STXri || in isStoreToStackSlot()
66 MI.getOpcode() == SP::STFri || MI.getOpcode() == SP::STDFri || in isStoreToStackSlot()
67 MI.getOpcode() == SP::STQFri) { in isStoreToStackSlot()
144 static bool isUncondBranchOpcode(int Opc) { return Opc == SP::BA; } in isUncondBranchOpcode()
147 return Opc == SP::FBCOND || Opc == SP::BCOND; in isCondBranchOpcode()
151 return Opc == SP::BINDrr || Opc == SP::BINDri; in isIndirectBranchOpcode()
[all …]
|
| D | DelaySlotFiller.cpp | 120 (MI->getOpcode() == SP::RESTORErr in runOnMachineBasicBlock()
121 || MI->getOpcode() == SP::RESTOREri)) { in runOnMachineBasicBlock()
129 (MI->getOpcode() == SP::FCMPS || MI->getOpcode() == SP::FCMPD in runOnMachineBasicBlock()
130 || MI->getOpcode() == SP::FCMPQ)) { in runOnMachineBasicBlock()
131 BuildMI(MBB, I, MI->getDebugLoc(), TII->get(SP::NOP)); in runOnMachineBasicBlock()
149 BuildMI(MBB, I, MI->getDebugLoc(), TII->get(SP::NOP)); in runOnMachineBasicBlock()
159 TII->get(SP::UNIMP)).addImm(structSize); in runOnMachineBasicBlock()
181 if (slot->getOpcode() == SP::RET || slot->getOpcode() == SP::TLS_CALL) in findDelayInstr()
184 if (slot->getOpcode() == SP::RETL) { in findDelayInstr()
188 if (J->getOpcode() == SP::RESTORErr in findDelayInstr()
[all …]
|
| D | LeonPasses.cpp | 52 for (int RegisterIndex = SP::F0; RegisterIndex <= SP::F31; ++RegisterIndex) { in getUnusedFPRegister()
89 if (Opcode >= SP::LDDArr && Opcode <= SP::LDrr) { in runOnMachineFunction()
91 BuildMI(MBB, NMBBI, DL, TII.get(SP::NOP)); in runOnMachineFunction()
99 BuildMI(MBB, NMBBI, DL, TII.get(SP::NOP)); in runOnMachineFunction()
146 if (Opcode == SP::FSMULD && MI.getNumOperands() == 3) { in runOnMachineFunction()
194 BuildMI(MBB, MBBI, DL, TII.get(SP::FSTOD)) in runOnMachineFunction()
199 BuildMI(MBB, MBBI, DL, TII.get(SP::FSTOD)) in runOnMachineFunction()
204 BuildMI(MBB, MBBI, DL, TII.get(SP::FMULD)) in runOnMachineFunction()
258 if (Opcode == SP::FMULS && MI.getNumOperands() == 3) { in runOnMachineFunction()
305 BuildMI(MBB, MBBI, DL, TII.get(SP::FSTOD)) in runOnMachineFunction()
[all …]
|
| /external/llvm-project/llvm/lib/Target/Sparc/ |
| D | SparcFrameLowering.cpp | 52 BuildMI(MBB, MBBI, dl, TII.get(ADDri), SP::O6) in emitSPAdjustment()
53 .addReg(SP::O6).addImm(NumBytes); in emitSPAdjustment()
64 BuildMI(MBB, MBBI, dl, TII.get(SP::SETHIi), SP::G1) in emitSPAdjustment()
66 BuildMI(MBB, MBBI, dl, TII.get(SP::ORri), SP::G1) in emitSPAdjustment()
67 .addReg(SP::G1).addImm(LO10(NumBytes)); in emitSPAdjustment()
68 BuildMI(MBB, MBBI, dl, TII.get(ADDrr), SP::O6) in emitSPAdjustment()
69 .addReg(SP::O6).addReg(SP::G1); in emitSPAdjustment()
77 BuildMI(MBB, MBBI, dl, TII.get(SP::SETHIi), SP::G1) in emitSPAdjustment()
79 BuildMI(MBB, MBBI, dl, TII.get(SP::XORri), SP::G1) in emitSPAdjustment()
80 .addReg(SP::G1).addImm(LOX10(NumBytes)); in emitSPAdjustment()
[all …]
|
| D | SparcRegisterInfo.cpp | 36 SparcRegisterInfo::SparcRegisterInfo() : SparcGenRegisterInfo(SP::O7) {} in SparcRegisterInfo()
58 Reserved.set(SP::G1); in getReservedRegs()
62 Reserved.set(SP::G2); in getReservedRegs()
63 Reserved.set(SP::G3); in getReservedRegs()
64 Reserved.set(SP::G4); in getReservedRegs()
68 Reserved.set(SP::G5); in getReservedRegs()
70 Reserved.set(SP::O6); in getReservedRegs()
71 Reserved.set(SP::I6); in getReservedRegs()
72 Reserved.set(SP::I7); in getReservedRegs()
73 Reserved.set(SP::G0); in getReservedRegs()
[all …]
|
| D | SparcInstrInfo.cpp | 35 : SparcGenInstrInfo(SP::ADJCALLSTACKDOWN, SP::ADJCALLSTACKUP), RI(), in SparcInstrInfo()
45 if (MI.getOpcode() == SP::LDri || MI.getOpcode() == SP::LDXri || in isLoadFromStackSlot()
46 MI.getOpcode() == SP::LDFri || MI.getOpcode() == SP::LDDFri || in isLoadFromStackSlot()
47 MI.getOpcode() == SP::LDQFri) { in isLoadFromStackSlot()
64 if (MI.getOpcode() == SP::STri || MI.getOpcode() == SP::STXri || in isStoreToStackSlot()
65 MI.getOpcode() == SP::STFri || MI.getOpcode() == SP::STDFri || in isStoreToStackSlot()
66 MI.getOpcode() == SP::STQFri) { in isStoreToStackSlot()
143 static bool isUncondBranchOpcode(int Opc) { return Opc == SP::BA; } in isUncondBranchOpcode()
146 return Opc == SP::FBCOND || Opc == SP::BCOND; in isCondBranchOpcode()
150 return Opc == SP::BINDrr || Opc == SP::BINDri; in isIndirectBranchOpcode()
[all …]
|
| D | DelaySlotFiller.cpp | 117 (MI->getOpcode() == SP::RESTORErr in runOnMachineBasicBlock()
118 || MI->getOpcode() == SP::RESTOREri)) { in runOnMachineBasicBlock()
126 (MI->getOpcode() == SP::FCMPS || MI->getOpcode() == SP::FCMPD in runOnMachineBasicBlock()
127 || MI->getOpcode() == SP::FCMPQ)) { in runOnMachineBasicBlock()
128 BuildMI(MBB, I, MI->getDebugLoc(), TII->get(SP::NOP)); in runOnMachineBasicBlock()
146 BuildMI(MBB, I, MI->getDebugLoc(), TII->get(SP::NOP)); in runOnMachineBasicBlock()
156 TII->get(SP::UNIMP)).addImm(structSize); in runOnMachineBasicBlock()
178 if (slot->getOpcode() == SP::RET || slot->getOpcode() == SP::TLS_CALL) in findDelayInstr()
181 if (slot->getOpcode() == SP::RETL) { in findDelayInstr()
185 if (J->getOpcode() == SP::RESTORErr in findDelayInstr()
[all …]
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Sparc/ |
| D | SparcFrameLowering.cpp | 52 BuildMI(MBB, MBBI, dl, TII.get(ADDri), SP::O6) in emitSPAdjustment()
53 .addReg(SP::O6).addImm(NumBytes); in emitSPAdjustment()
64 BuildMI(MBB, MBBI, dl, TII.get(SP::SETHIi), SP::G1) in emitSPAdjustment()
66 BuildMI(MBB, MBBI, dl, TII.get(SP::ORri), SP::G1) in emitSPAdjustment()
67 .addReg(SP::G1).addImm(LO10(NumBytes)); in emitSPAdjustment()
68 BuildMI(MBB, MBBI, dl, TII.get(ADDrr), SP::O6) in emitSPAdjustment()
69 .addReg(SP::O6).addReg(SP::G1); in emitSPAdjustment()
77 BuildMI(MBB, MBBI, dl, TII.get(SP::SETHIi), SP::G1) in emitSPAdjustment()
79 BuildMI(MBB, MBBI, dl, TII.get(SP::XORri), SP::G1) in emitSPAdjustment()
80 .addReg(SP::G1).addImm(LOX10(NumBytes)); in emitSPAdjustment()
[all …]
|
| D | SparcRegisterInfo.cpp | 36 SparcRegisterInfo::SparcRegisterInfo() : SparcGenRegisterInfo(SP::O7) {} in SparcRegisterInfo()
58 Reserved.set(SP::G1); in getReservedRegs()
62 Reserved.set(SP::G2); in getReservedRegs()
63 Reserved.set(SP::G3); in getReservedRegs()
64 Reserved.set(SP::G4); in getReservedRegs()
68 Reserved.set(SP::G5); in getReservedRegs()
70 Reserved.set(SP::O6); in getReservedRegs()
71 Reserved.set(SP::I6); in getReservedRegs()
72 Reserved.set(SP::I7); in getReservedRegs()
73 Reserved.set(SP::G0); in getReservedRegs()
[all …]
|
| D | SparcInstrInfo.cpp | 35 : SparcGenInstrInfo(SP::ADJCALLSTACKDOWN, SP::ADJCALLSTACKUP), RI(), in SparcInstrInfo()
45 if (MI.getOpcode() == SP::LDri || MI.getOpcode() == SP::LDXri || in isLoadFromStackSlot()
46 MI.getOpcode() == SP::LDFri || MI.getOpcode() == SP::LDDFri || in isLoadFromStackSlot()
47 MI.getOpcode() == SP::LDQFri) { in isLoadFromStackSlot()
64 if (MI.getOpcode() == SP::STri || MI.getOpcode() == SP::STXri || in isStoreToStackSlot()
65 MI.getOpcode() == SP::STFri || MI.getOpcode() == SP::STDFri || in isStoreToStackSlot()
66 MI.getOpcode() == SP::STQFri) { in isStoreToStackSlot()
143 static bool isUncondBranchOpcode(int Opc) { return Opc == SP::BA; } in isUncondBranchOpcode()
146 return Opc == SP::FBCOND || Opc == SP::BCOND; in isCondBranchOpcode()
150 return Opc == SP::BINDrr || Opc == SP::BINDri; in isIndirectBranchOpcode()
[all …]
|
| D | DelaySlotFiller.cpp | 117 (MI->getOpcode() == SP::RESTORErr in runOnMachineBasicBlock()
118 || MI->getOpcode() == SP::RESTOREri)) { in runOnMachineBasicBlock()
126 (MI->getOpcode() == SP::FCMPS || MI->getOpcode() == SP::FCMPD in runOnMachineBasicBlock()
127 || MI->getOpcode() == SP::FCMPQ)) { in runOnMachineBasicBlock()
128 BuildMI(MBB, I, MI->getDebugLoc(), TII->get(SP::NOP)); in runOnMachineBasicBlock()
146 BuildMI(MBB, I, MI->getDebugLoc(), TII->get(SP::NOP)); in runOnMachineBasicBlock()
156 TII->get(SP::UNIMP)).addImm(structSize); in runOnMachineBasicBlock()
178 if (slot->getOpcode() == SP::RET || slot->getOpcode() == SP::TLS_CALL) in findDelayInstr()
181 if (slot->getOpcode() == SP::RETL) { in findDelayInstr()
185 if (J->getOpcode() == SP::RESTORErr in findDelayInstr()
[all …]
|
| /external/llvm/test/CodeGen/Mips/cconv/ |
| D | arguments-varargs.ll | 23 ; O32: addiu [[SP:\$sp]], $sp, -8
24 ; N32: addiu [[SP:\$sp]], $sp, -64
25 ; N64: daddiu [[SP:\$sp]], $sp, -64
28 ; O32-DAG: sw $7, 20([[SP]])
29 ; O32-DAG: sw $6, 16([[SP]])
30 ; O32-DAG: sw $5, 12([[SP]])
32 ; NEW-DAG: sd $11, 56([[SP]])
33 ; NEW-DAG: sd $10, 48([[SP]])
34 ; NEW-DAG: sd $9, 40([[SP]])
35 ; NEW-DAG: sd $8, 32([[SP]])
[all …]
|
| /external/llvm-project/llvm/test/CodeGen/Mips/cconv/ |
| D | arguments-varargs.ll | 31 ; O32: addiu [[SP:\$sp]], $sp, -8
32 ; N32: addiu [[SP:\$sp]], $sp, -64
33 ; N64: daddiu [[SP:\$sp]], $sp, -64
36 ; O32-DAG: sw $7, 20([[SP]])
37 ; O32-DAG: sw $6, 16([[SP]])
38 ; O32-DAG: sw $5, 12([[SP]])
40 ; NEW-DAG: sd $11, 56([[SP]])
41 ; NEW-DAG: sd $10, 48([[SP]])
42 ; NEW-DAG: sd $9, 40([[SP]])
43 ; NEW-DAG: sd $8, 32([[SP]])
[all …]
|
| /external/icu/icu4c/source/test/testdata/ |
| D | LineBreakTest.txt | 30 × 0023 × 0020 ÷ 0023 ÷ # × [0.3] NUMBER SIGN (AL) × [7.01] SPACE (SP) ÷ [18.0] NUMBER SIGN (AL) ÷ …
32 …0.3] NUMBER SIGN (AL) × [9.0] COMBINING DIAERESIS (CM1_CM) × [7.01] SPACE (SP) ÷ [18.0] NUMBER SIG…
34 × 0023 × 0020 ÷ 2014 ÷ # × [0.3] NUMBER SIGN (AL) × [7.01] SPACE (SP) ÷ [18.0] EM DASH (B2) ÷ [0.3]
36 …0.3] NUMBER SIGN (AL) × [9.0] COMBINING DIAERESIS (CM1_CM) × [7.01] SPACE (SP) ÷ [18.0] EM DASH (B…
38 × 0023 × 0020 ÷ 0009 ÷ # × [0.3] NUMBER SIGN (AL) × [7.01] SPACE (SP) ÷ [18.0] <CHARACTER TABULATI…
40 …0.3] NUMBER SIGN (AL) × [9.0] COMBINING DIAERESIS (CM1_CM) × [7.01] SPACE (SP) ÷ [18.0] <CHARACTER…
42 × 0023 × 0020 ÷ 00B4 ÷ # × [0.3] NUMBER SIGN (AL) × [7.01] SPACE (SP) ÷ [18.0] ACUTE ACCENT (BB) ÷…
44 …0.3] NUMBER SIGN (AL) × [9.0] COMBINING DIAERESIS (CM1_CM) × [7.01] SPACE (SP) ÷ [18.0] ACUTE ACCE…
46 × 0023 × 0020 × 000B ÷ # × [0.3] NUMBER SIGN (AL) × [7.01] SPACE (SP) × [6.0] <LINE TABULATION> (B…
48 …0.3] NUMBER SIGN (AL) × [9.0] COMBINING DIAERESIS (CM1_CM) × [7.01] SPACE (SP) × [6.0] <LINE TABUL…
[all …]
|
| /external/cldr/tools/java/org/unicode/cldr/util/data/external/ |
| D | world_bank_data.csv | 2 Afghanistan,AFG,"Population, total",SP.POP.TOTL,20779953,21606988,22600770,23680871,24726684,256542…
4 Albania,ALB,"Population, total",SP.POP.TOTL,3089027,3060173,3051010,3039616,3026939,3011487,2992547…
6 Algeria,DZA,"Population, total",SP.POP.TOTL,31042235,31451514,31855109,32264157,32692163,33149724,3…
8 American Samoa,ASM,"Population, total",SP.POP.TOTL,57821,58494,59080,59504,59681,59562,59107,58365,…
10 Andorra,AND,"Population, total",SP.POP.TOTL,65390,67341,70049,73182,76244,78867,80993,82684,83862,8…
12 Angola,AGO,"Population, total",SP.POP.TOTL,16395473,16945753,17519417,18121479,18758145,19433602,20…
14 Antigua and Barbuda,ATG,"Population, total",SP.POP.TOTL,76016,77212,78295,79300,80336,81465,82704,8…
16 Argentina,ARG,"Population, total",SP.POP.TOTL,36870787,37275652,37681749,38087868,38491972,38892931…
18 Armenia,ARM,"Population, total",SP.POP.TOTL,3069591,3050687,3033978,3017932,3000720,2981269,2958307…
20 Aruba,ABW,"Population, total",SP.POP.TOTL,90853,92898,94992,97017,98737,100031,100834,101222,101358…
[all …]
|
| /external/libxaac/decoder/armv7/ |
| D | ixheaacd_cos_sin_mod.s | 40 STMFD SP!, {R4-R12, R14}
51 SUB R10, SP, #516
52 SUB SP, SP, #516
64 STMFD SP!, {R0-R3}
218 LDR R1, [SP, #4]
220 LDR R4, [SP, #8]
221 LDR R0, [SP, #8]
222 ADD R1, SP, #16
231 LDR R5, [SP, #12]
243 LDR R3, [SP]
[all …]
|