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Searched refs:SPSR_fsxc (Results 1 – 14 of 14) sorted by relevance

/external/llvm/test/CodeGen/ARM/
Dspecial-reg-acore.ll42 ; ACORE: msr SPSR_fsxc, r0
/external/llvm-project/llvm/test/CodeGen/ARM/
Dspecial-reg-acore.ll42 ; ACORE: msr SPSR_fsxc, r0
/external/vixl/src/aarch32/
Dinstructions-aarch32.cc280 case SPSR_fsxc: in GetName()
Dinstructions-aarch32.h872 SPSR_fsxc = 0x1f enumerator
880 VIXL_ASSERT(reg <= SPSR_fsxc); in MaskedSpecialRegister()
/external/llvm-project/llvm/test/MC/ARM/
Dbasic-arm-instructions.s1467 msr SPSR_fsxc, #5
1472 msr SPSR_fsxc, #40, #2
1473 msr SPSR_fsxc, $40, $2
1474 msr SPSR_fsxc, 40, 2
1475 msr SPSR_fsxc, (2 * 20), (1 << 1)
1491 @ CHECK: msr SPSR_fsxc, #5 @ encoding: [0x05,0xf0,0x6f,0xe3]
1496 @ CHECK: msr SPSR_fsxc, #40, #2 @ encoding: [0x28,0xf1,0x6f,0xe3]
1497 @ CHECK: msr SPSR_fsxc, #40, #2 @ encoding: [0x28,0xf1,0x6f,0xe3]
1498 @ CHECK: msr SPSR_fsxc, #40, #2 @ encoding: [0x28,0xf1,0x6f,0xe3]
1499 @ CHECK: msr SPSR_fsxc, #40, #2 @ encoding: [0x28,0xf1,0x6f,0xe3]
[all …]
Dbasic-thumb2-instructions.s1766 msr SPSR_fsxc, r5
1782 @ CHECK: msr SPSR_fsxc, r5 @ encoding: [0x95,0xf3,0x00,0x8f]
/external/llvm/test/MC/ARM/
Dbasic-arm-instructions.s1437 msr SPSR_fsxc, #5
1442 msr SPSR_fsxc, #40, #2
1443 msr SPSR_fsxc, $40, $2
1444 msr SPSR_fsxc, 40, 2
1445 msr SPSR_fsxc, (2 * 20), (1 << 1)
1461 @ CHECK: msr SPSR_fsxc, #5 @ encoding: [0x05,0xf0,0x6f,0xe3]
1466 @ CHECK: msr SPSR_fsxc, #40, #2 @ encoding: [0x28,0xf1,0x6f,0xe3]
1467 @ CHECK: msr SPSR_fsxc, #40, #2 @ encoding: [0x28,0xf1,0x6f,0xe3]
1468 @ CHECK: msr SPSR_fsxc, #40, #2 @ encoding: [0x28,0xf1,0x6f,0xe3]
1469 @ CHECK: msr SPSR_fsxc, #40, #2 @ encoding: [0x28,0xf1,0x6f,0xe3]
[all …]
Dbasic-thumb2-instructions.s1571 msr SPSR_fsxc, r5
1587 @ CHECK: msr SPSR_fsxc, r5 @ encoding: [0x95,0xf3,0x00,0x8f]
/external/llvm-project/llvm/test/tools/llvm-mca/ARM/
Dcortex-a57-basic-instructions.s320 msr SPSR_fsxc, #5
323 msr SPSR_fsxc, #40, #2
336 msr SPSR_fsxc, r0
1190 # CHECK-NEXT: 0 0 0.00 U msr SPSR_fsxc, #5
1193 # CHECK-NEXT: 0 0 0.00 U msr SPSR_fsxc, #40, #2
1206 # CHECK-NEXT: 0 0 0.00 U msr SPSR_fsxc, r0
2067 # CHECK-NEXT: - - - - - - - - msr SPSR_fsxc, #5
2070 # CHECK-NEXT: - - - - - - - - msr SPSR_fsxc, #40, #2
2083 # CHECK-NEXT: - - - - - - - - msr SPSR_fsxc, r0
Dcortex-a57-thumb.s404 msr SPSR_fsxc, r5
1312 # CHECK-NEXT: 0 0 0.00 U msr SPSR_fsxc, r5
2226 # CHECK-NEXT: - - - - - - - - msr SPSR_fsxc, r5
/external/llvm-project/llvm/test/MC/Disassembler/ARM/
Dbasic-arm-instructions.txt860 # CHECK: msr SPSR_fsxc, #5
863 # CHECK: msr SPSR_fsxc, #40, #2
894 # CHECK: msr SPSR_fsxc, r0
Dthumb2.txt1130 # CHECK: msr SPSR_fsxc, r5
/external/llvm/test/MC/Disassembler/ARM/
Dbasic-arm-instructions.txt860 # CHECK: msr SPSR_fsxc, #5
863 # CHECK: msr SPSR_fsxc, #40, #2
894 # CHECK: msr SPSR_fsxc, r0
Dthumb2.txt1130 # CHECK: msr SPSR_fsxc, r5