1 /* 2 * Copyright (c) 2018-2020, Arm Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef SGI_BASE_PLATFORM_DEF_H 8 #define SGI_BASE_PLATFORM_DEF_H 9 10 #include <lib/utils_def.h> 11 #include <lib/xlat_tables/xlat_tables_defs.h> 12 #include <plat/arm/common/arm_def.h> 13 #include <plat/arm/common/arm_spm_def.h> 14 #include <plat/arm/css/common/css_def.h> 15 #include <plat/common/common_def.h> 16 17 #define PLATFORM_CORE_COUNT (CSS_SGI_CHIP_COUNT * \ 18 PLAT_ARM_CLUSTER_COUNT * \ 19 CSS_SGI_MAX_CPUS_PER_CLUSTER * \ 20 CSS_SGI_MAX_PE_PER_CPU) 21 22 #define PLAT_ARM_TRUSTED_SRAM_SIZE 0x00040000 /* 256 KB */ 23 24 /* Remote chip address offset (4TB per chip) */ 25 #define CSS_SGI_REMOTE_CHIP_MEM_OFFSET(n) ((ULL(1) << 42) * (n)) 26 27 /* 28 * PLAT_ARM_MMAP_ENTRIES depends on the number of entries in the 29 * plat_arm_mmap array defined for each BL stage. 30 */ 31 #if defined(IMAGE_BL31) 32 # if SPM_MM 33 # define PLAT_ARM_MMAP_ENTRIES 9 34 # define MAX_XLAT_TABLES 7 35 # define PLAT_SP_IMAGE_MMAP_REGIONS 7 36 # define PLAT_SP_IMAGE_MAX_XLAT_TABLES 10 37 # else 38 # define PLAT_ARM_MMAP_ENTRIES (5 + ((CSS_SGI_CHIP_COUNT - 1) * 3)) 39 # define MAX_XLAT_TABLES (6 + ((CSS_SGI_CHIP_COUNT - 1) * 3)) 40 # endif 41 #elif defined(IMAGE_BL32) 42 # define PLAT_ARM_MMAP_ENTRIES 8 43 # define MAX_XLAT_TABLES 5 44 #elif !USE_ROMLIB 45 # define PLAT_ARM_MMAP_ENTRIES 11 46 # define MAX_XLAT_TABLES 7 47 #else 48 # define PLAT_ARM_MMAP_ENTRIES 12 49 # define MAX_XLAT_TABLES 6 50 #endif 51 52 /* 53 * PLAT_ARM_MAX_BL1_RW_SIZE is calculated using the current BL1 RW debug size 54 * plus a little space for growth. 55 */ 56 #define PLAT_ARM_MAX_BL1_RW_SIZE 0xC000 57 58 /* 59 * PLAT_ARM_MAX_ROMLIB_RW_SIZE is define to use a full page 60 */ 61 62 #if USE_ROMLIB 63 #define PLAT_ARM_MAX_ROMLIB_RW_SIZE 0x1000 64 #define PLAT_ARM_MAX_ROMLIB_RO_SIZE 0xe000 65 #else 66 #define PLAT_ARM_MAX_ROMLIB_RW_SIZE 0 67 #define PLAT_ARM_MAX_ROMLIB_RO_SIZE 0 68 #endif 69 70 /* 71 * PLAT_ARM_MAX_BL2_SIZE is calculated using the current BL2 debug size plus a 72 * little space for growth. 73 */ 74 #if TRUSTED_BOARD_BOOT 75 # define PLAT_ARM_MAX_BL2_SIZE 0x1D000 76 #else 77 # define PLAT_ARM_MAX_BL2_SIZE 0x14000 78 #endif 79 80 /* 81 * Since BL31 NOBITS overlays BL2 and BL1-RW, PLAT_ARM_MAX_BL31_SIZE is 82 * calculated using the current BL31 PROGBITS debug size plus the sizes of 83 * BL2 and BL1-RW 84 */ 85 #define PLAT_ARM_MAX_BL31_SIZE 0x3B000 86 87 /* 88 * Size of cacheable stacks 89 */ 90 #if defined(IMAGE_BL1) 91 # if TRUSTED_BOARD_BOOT 92 # define PLATFORM_STACK_SIZE 0x1000 93 # else 94 # define PLATFORM_STACK_SIZE 0x440 95 # endif 96 #elif defined(IMAGE_BL2) 97 # if TRUSTED_BOARD_BOOT 98 # define PLATFORM_STACK_SIZE 0x1000 99 # else 100 # define PLATFORM_STACK_SIZE 0x400 101 # endif 102 #elif defined(IMAGE_BL2U) 103 # define PLATFORM_STACK_SIZE 0x400 104 #elif defined(IMAGE_BL31) 105 # if SPM_MM 106 # define PLATFORM_STACK_SIZE 0x500 107 # else 108 # define PLATFORM_STACK_SIZE 0x400 109 # endif 110 #elif defined(IMAGE_BL32) 111 # define PLATFORM_STACK_SIZE 0x440 112 #endif 113 114 115 #define PLAT_ARM_NSTIMER_FRAME_ID 0 116 117 #define PLAT_ARM_TRUSTED_ROM_BASE 0x0 118 #define PLAT_ARM_TRUSTED_ROM_SIZE 0x00080000 /* 512KB */ 119 120 #define PLAT_ARM_NSRAM_BASE 0x06000000 121 #define PLAT_ARM_NSRAM_SIZE 0x00080000 /* 512KB */ 122 123 #define PLAT_ARM_DRAM2_BASE ULL(0x8080000000) 124 #define PLAT_ARM_DRAM2_SIZE ULL(0x180000000) 125 126 #define PLAT_ARM_G1S_IRQ_PROPS(grp) CSS_G1S_IRQ_PROPS(grp) 127 #define PLAT_ARM_G0_IRQ_PROPS(grp) ARM_G0_IRQ_PROPS(grp) 128 129 #define CSS_SGI_DEVICE_BASE (0x20000000) 130 #define CSS_SGI_DEVICE_SIZE (0x20000000) 131 #define CSS_SGI_MAP_DEVICE MAP_REGION_FLAT( \ 132 CSS_SGI_DEVICE_BASE, \ 133 CSS_SGI_DEVICE_SIZE, \ 134 MT_DEVICE | MT_RW | MT_SECURE) 135 136 #define ARM_MAP_SHARED_RAM_REMOTE_CHIP(n) \ 137 MAP_REGION_FLAT( \ 138 CSS_SGI_REMOTE_CHIP_MEM_OFFSET(n) + \ 139 ARM_SHARED_RAM_BASE, \ 140 ARM_SHARED_RAM_SIZE, \ 141 MT_NON_CACHEABLE | MT_RW | MT_SECURE \ 142 ) 143 144 #define CSS_SGI_MAP_DEVICE_REMOTE_CHIP(n) \ 145 MAP_REGION_FLAT( \ 146 CSS_SGI_REMOTE_CHIP_MEM_OFFSET(n) + \ 147 CSS_SGI_DEVICE_BASE, \ 148 CSS_SGI_DEVICE_SIZE, \ 149 MT_DEVICE | MT_RW | MT_SECURE \ 150 ) 151 152 #define SOC_CSS_MAP_DEVICE_REMOTE_CHIP(n) \ 153 MAP_REGION_FLAT( \ 154 CSS_SGI_REMOTE_CHIP_MEM_OFFSET(n) + \ 155 SOC_CSS_DEVICE_BASE, \ 156 SOC_CSS_DEVICE_SIZE, \ 157 MT_DEVICE | MT_RW | MT_SECURE \ 158 ) 159 160 /* Map the secure region for access from S-EL0 */ 161 #define PLAT_ARM_SECURE_MAP_DEVICE MAP_REGION_FLAT( \ 162 SOC_CSS_DEVICE_BASE, \ 163 SOC_CSS_DEVICE_SIZE, \ 164 MT_DEVICE | MT_RW | MT_SECURE | MT_USER) 165 166 #define PLAT_SP_PRI PLAT_RAS_PRI 167 168 #if RAS_EXTENSION 169 /* Allocate 128KB for CPER buffers */ 170 #define PLAT_SP_BUF_BASE ULL(0x20000) 171 172 #define PLAT_ARM_SP_IMAGE_STACK_BASE (PLAT_SP_IMAGE_NS_BUF_BASE + \ 173 PLAT_SP_IMAGE_NS_BUF_SIZE + \ 174 PLAT_SP_BUF_BASE) 175 176 /* Platform specific SMC FID's used for RAS */ 177 #define SP_DMC_ERROR_INJECT_EVENT_AARCH64 0xC4000042 178 #define SP_DMC_ERROR_INJECT_EVENT_AARCH32 0x84000042 179 180 #define SP_DMC_ERROR_OVERFLOW_EVENT_AARCH64 0xC4000043 181 #define SP_DMC_ERROR_OVERFLOW_EVENT_AARCH32 0x84000043 182 183 #define SP_DMC_ERROR_ECC_EVENT_AARCH64 0xC4000044 184 #define SP_DMC_ERROR_ECC_EVENT_AARCH32 0x84000044 185 186 /* ARM SDEI dynamic shared event numbers */ 187 #define SGI_SDEI_DS_EVENT_0 804 188 #define SGI_SDEI_DS_EVENT_1 805 189 190 #define PLAT_ARM_PRIVATE_SDEI_EVENTS \ 191 SDEI_DEFINE_EVENT_0(ARM_SDEI_SGI), \ 192 SDEI_EXPLICIT_EVENT(SGI_SDEI_DS_EVENT_0, SDEI_MAPF_CRITICAL), \ 193 SDEI_EXPLICIT_EVENT(SGI_SDEI_DS_EVENT_1, SDEI_MAPF_CRITICAL), 194 #define PLAT_ARM_SHARED_SDEI_EVENTS 195 196 #define ARM_SP_CPER_BUF_BASE (PLAT_SP_IMAGE_NS_BUF_BASE + \ 197 PLAT_SP_IMAGE_NS_BUF_SIZE) 198 #define ARM_SP_CPER_BUF_SIZE ULL(0x20000) 199 #define ARM_SP_CPER_BUF_MMAP MAP_REGION2( \ 200 ARM_SP_CPER_BUF_BASE, \ 201 ARM_SP_CPER_BUF_BASE, \ 202 ARM_SP_CPER_BUF_SIZE, \ 203 MT_RW_DATA | MT_NS | MT_USER, \ 204 PAGE_SIZE) 205 206 #else 207 #define PLAT_ARM_SP_IMAGE_STACK_BASE (PLAT_SP_IMAGE_NS_BUF_BASE + \ 208 PLAT_SP_IMAGE_NS_BUF_SIZE) 209 #endif /* RAS_EXTENSION */ 210 211 /* Platform ID address */ 212 #define SSC_VERSION (SSC_REG_BASE + SSC_VERSION_OFFSET) 213 #ifndef __ASSEMBLER__ 214 /* SSC_VERSION related accessors */ 215 /* Returns the part number of the platform */ 216 #define GET_SGI_PART_NUM \ 217 GET_SSC_VERSION_PART_NUM(mmio_read_32(SSC_VERSION)) 218 /* Returns the configuration number of the platform */ 219 #define GET_SGI_CONFIG_NUM \ 220 GET_SSC_VERSION_CONFIG(mmio_read_32(SSC_VERSION)) 221 #endif /* __ASSEMBLER__ */ 222 223 /******************************************************************************* 224 * Memprotect definitions 225 ******************************************************************************/ 226 /* PSCI memory protect definitions: 227 * This variable is stored in a non-secure flash because some ARM reference 228 * platforms do not have secure NVRAM. Real systems that provided MEM_PROTECT 229 * support must use a secure NVRAM to store the PSCI MEM_PROTECT definitions. 230 */ 231 #define PLAT_ARM_MEM_PROT_ADDR (V2M_FLASH0_BASE + \ 232 V2M_FLASH0_SIZE - V2M_FLASH_BLOCK_SIZE) 233 234 /*Secure Watchdog Constants */ 235 #define SBSA_SECURE_WDOG_BASE UL(0x2A480000) 236 #define SBSA_SECURE_WDOG_TIMEOUT UL(100) 237 238 /* Number of SCMI channels on the platform */ 239 #define PLAT_ARM_SCMI_CHANNEL_COUNT CSS_SGI_CHIP_COUNT 240 241 #endif /* SGI_BASE_PLATFORM_DEF_H */ 242