| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Lanai/ |
| D | LanaiAluCode.h | 37 SRA = 0x37, enumerator
96 case SRA: in lanaiAluCodeToString()
114 .Case("sha", SRA) in stringToLanaiAluCode()
138 case ISD::SRA: in isdToLanaiAluCode()
139 return AluCode::SRA; in isdToLanaiAluCode()
|
| /external/llvm-project/llvm/lib/Target/Lanai/ |
| D | LanaiAluCode.h | 37 SRA = 0x37, enumerator
96 case SRA: in lanaiAluCodeToString()
114 .Case("sha", SRA) in stringToLanaiAluCode()
138 case ISD::SRA: in isdToLanaiAluCode()
139 return AluCode::SRA; in isdToLanaiAluCode()
|
| /external/llvm/lib/Target/Lanai/ |
| D | LanaiAluCode.h | 38 SRA = 0x37, enumerator
97 case SRA: in lanaiAluCodeToString()
115 .Case("sha", SRA) in stringToLanaiAluCode()
139 case ISD::SRA: in isdToLanaiAluCode()
140 return AluCode::SRA; in isdToLanaiAluCode()
|
| /external/llvm/lib/Target/X86/ |
| D | X86TargetTransformInfo.cpp | 119 { ISD::SRA, MVT::v4i64, 4 }, // 2 x psrad + shuffle. in getArithmeticInstrCost()
137 { ISD::SRA, MVT::v16i32, 1 }, in getArithmeticInstrCost()
140 { ISD::SRA, MVT::v8i64, 1 }, in getArithmeticInstrCost()
153 { ISD::SRA, MVT::v4i32, 1 }, in getArithmeticInstrCost()
156 { ISD::SRA, MVT::v8i32, 1 }, in getArithmeticInstrCost()
180 { ISD::SRA, MVT::v16i8, 2 }, in getArithmeticInstrCost()
183 { ISD::SRA, MVT::v8i16, 2 }, in getArithmeticInstrCost()
186 { ISD::SRA, MVT::v4i32, 2 }, in getArithmeticInstrCost()
189 { ISD::SRA, MVT::v2i64, 2 }, in getArithmeticInstrCost()
193 { ISD::SRA, MVT::v32i8, 4 }, in getArithmeticInstrCost()
[all …]
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/ |
| D | X86TargetTransformInfo.cpp | 293 { ISD::SRA, MVT::v64i8, 4 }, // psrlw, pand, pxor, psubb. in getArithmeticInstrCost()
304 { ISD::SRA, MVT::v2i64, 1 }, in getArithmeticInstrCost()
305 { ISD::SRA, MVT::v4i64, 1 }, in getArithmeticInstrCost()
306 { ISD::SRA, MVT::v8i64, 1 }, in getArithmeticInstrCost()
319 { ISD::SRA, MVT::v32i8, 4 }, // psrlw, pand, pxor, psubb. in getArithmeticInstrCost()
321 { ISD::SRA, MVT::v4i64, 4 }, // 2 x psrad + shuffle. in getArithmeticInstrCost()
334 { ISD::SRA, MVT::v16i8, 4 }, // psrlw, pand, pxor, psubb. in getArithmeticInstrCost()
338 { ISD::SRA, MVT::v32i8, 8+2 }, // 2*(psrlw, pand, pxor, psubb) + split. in getArithmeticInstrCost()
453 { ISD::SRA, MVT::v16i16, 1 }, // psraw. in getArithmeticInstrCost()
474 { ISD::SRA, MVT::v8i16, 1 }, // psraw. in getArithmeticInstrCost()
[all …]
|
| /external/llvm-project/llvm/lib/Target/X86/ |
| D | X86TargetTransformInfo.cpp | 306 { ISD::SRA, MVT::v64i8, 4 }, // psrlw, pand, pxor, psubb. in getArithmeticInstrCost()
317 { ISD::SRA, MVT::v2i64, 1 }, in getArithmeticInstrCost()
318 { ISD::SRA, MVT::v4i64, 1 }, in getArithmeticInstrCost()
319 { ISD::SRA, MVT::v8i64, 1 }, in getArithmeticInstrCost()
323 { ISD::SRA, MVT::v64i8, 8 }, // psrlw, pand, pxor, psubb. in getArithmeticInstrCost()
341 { ISD::SRA, MVT::v32i8, 4 }, // psrlw, pand, pxor, psubb. in getArithmeticInstrCost()
343 { ISD::SRA, MVT::v4i64, 4 }, // 2 x psrad + shuffle. in getArithmeticInstrCost()
361 { ISD::SRA, MVT::v16i8, 4 }, // psrlw, pand, pxor, psubb. in getArithmeticInstrCost()
365 { ISD::SRA, MVT::v32i8, 8+2 }, // 2*(psrlw, pand, pxor, psubb) + split. in getArithmeticInstrCost()
496 { ISD::SRA, MVT::v8i16, 1 }, // vpsravw in getArithmeticInstrCost()
[all …]
|
| /external/llvm/test/CodeGen/SystemZ/ |
| D | shift-09.ll | 45 ; Check that we use SRAK over SRA where useful.
55 ; Check that we use SRA over SRAK where possible.
|
| D | shift-03.ll | 5 ; Check the low end of the SRA range.
14 ; Check the high end of the defined SRA range.
|
| /external/llvm-project/llvm/test/CodeGen/SystemZ/ |
| D | shift-09.ll | 50 ; Check that we use SRAK over SRA where useful.
61 ; Check that we use SRA over SRAK where possible.
|
| D | shift-03.ll | 6 ; Check the low end of the SRA range.
16 ; Check the high end of the defined SRA range.
|
| /external/pcre/dist2/src/sljit/ |
| D | sljitNativeSPARC_32.c | 60 return push_inst(compiler, SRA | D(dst) | S1(dst) | IMM(24), DR(dst)); in emit_single_op()
71 …return push_inst(compiler, (op == SLJIT_MOV_S16 ? SRA : SRL) | D(dst) | S1(dst) | IMM(16), DR(dst)… in emit_single_op()
111 FAIL_IF(push_inst(compiler, SRA | D(TMP_REG1) | S1(dst) | IMM(31), DR(TMP_REG1))); in emit_single_op()
133 FAIL_IF(push_inst(compiler, SRA | D(dst) | S1(src1) | ARG2(flags, src2), DR(dst))); in emit_single_op()
|
| /external/llvm/test/CodeGen/X86/ |
| D | pr14204.ll | 4 ; SLL/SRA.
|
| /external/llvm-project/llvm/test/MC/Mips/mips1/ |
| D | valid.s | 132 # CHECK-NEXT: # <MCInst #{{[0-9]+}} SRA
135 # CHECK-NEXT: # <MCInst #{{[0-9]+}} SRA
138 # CHECK-NEXT: # <MCInst #{{[0-9]+}} SRA
141 # CHECK-NEXT: # <MCInst #{{[0-9]+}} SRA
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/ |
| D | ARMSelectionDAGInfo.h | 28 case ISD::SRA: return ARM_AM::asr; in getShiftOpcForNode()
|
| /external/llvm-project/llvm/lib/Target/ARM/ |
| D | ARMSelectionDAGInfo.h | 28 case ISD::SRA: return ARM_AM::asr; in getShiftOpcForNode()
|
| /external/llvm/lib/Target/ARM/ |
| D | ARMSelectionDAGInfo.h | 29 case ISD::SRA: return ARM_AM::asr; in getShiftOpcForNode()
|
| /external/llvm-project/llvm/test/Transforms/GlobalOpt/ |
| D | globalsra-multigep.ll | 7 ; We cannot SRA here due to the second gep meaning the access to g_data may be to either element
|
| /external/llvm-project/llvm/lib/Target/SystemZ/ |
| D | SystemZSelectionDAGInfo.cpp | 175 SDValue SRA = DAG.getNode(ISD::SRA, DL, MVT::i32, SHL, in addIPMSequence() local
177 return SRA; in addIPMSequence()
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/SystemZ/ |
| D | SystemZSelectionDAGInfo.cpp | 174 SDValue SRA = DAG.getNode(ISD::SRA, DL, MVT::i32, SHL, in addIPMSequence() local
176 return SRA; in addIPMSequence()
|
| /external/llvm-project/llvm/test/MC/Mips/mips2/ |
| D | valid.s | 173 # CHECK-NEXT: # <MCInst #{{[0-9]+}} SRA
176 # CHECK-NEXT: # <MCInst #{{[0-9]+}} SRA
179 # CHECK-NEXT: # <MCInst #{{[0-9]+}} SRA
182 # CHECK-NEXT: # <MCInst #{{[0-9]+}} SRA
|
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | LegalizeIntegerTypes.cpp | 86 case ISD::SRA: Res = PromoteIntRes_SRA(N); break; in PromoteIntegerResult()
678 return DAG.getNode(ISD::SRA, SDLoc(N), LHS.getValueType(), LHS, RHS); in PromoteIntRes_SRA()
919 case ISD::SRA: in PromoteIntegerOperand()
1394 case ISD::SRA: in ExpandIntegerResult()
1484 assert(N->getOpcode() == ISD::SRA && "Unknown shift!"); in ExpandShiftByConstant()
1486 Hi = Lo = DAG.getNode(ISD::SRA, DL, NVT, InH, in ExpandShiftByConstant()
1489 Lo = DAG.getNode(ISD::SRA, DL, NVT, InH, in ExpandShiftByConstant()
1491 Hi = DAG.getNode(ISD::SRA, DL, NVT, InH, in ExpandShiftByConstant()
1495 Hi = DAG.getNode(ISD::SRA, DL, NVT, InH, in ExpandShiftByConstant()
1503 Hi = DAG.getNode(ISD::SRA, DL, NVT, InH, DAG.getConstant(Amt, DL, ShTy)); in ExpandShiftByConstant()
[all …]
|
| /external/llvm-project/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/ |
| D | bitwise.mir | 270 ; MIPS32: [[SRA:%[0-9]+]]:gpr32 = SRA [[COPY]], 1
271 ; MIPS32: $v0 = COPY [[SRA]]
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/SelectionDAG/ |
| D | LegalizeIntegerTypes.cpp | 89 case ISD::SRA: Res = PromoteIntRes_SRA(N); break; in PromoteIntegerResult()
696 ShiftOp = ISD::SRA; in PromoteIntRes_ADDSUBSAT()
776 unsigned ShiftOp = Signed ? ISD::SRA : ISD::SRL; in PromoteIntRes_MULFIX()
990 return DAG.getNode(ISD::SRA, SDLoc(N), LHS.getValueType(), LHS, RHS); in PromoteIntRes_SRA()
1291 case ISD::SRA: in PromoteIntegerOperand()
1896 case ISD::SRA: in ExpandIntegerResult()
2013 assert(N->getOpcode() == ISD::SRA && "Unknown shift!"); in ExpandShiftByConstant()
2015 Hi = Lo = DAG.getNode(ISD::SRA, DL, NVT, InH, in ExpandShiftByConstant()
2018 Lo = DAG.getNode(ISD::SRA, DL, NVT, InH, in ExpandShiftByConstant()
2020 Hi = DAG.getNode(ISD::SRA, DL, NVT, InH, in ExpandShiftByConstant()
[all …]
|
| /external/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| D | LegalizeIntegerTypes.cpp | 90 case ISD::SRA: Res = PromoteIntRes_SRA(N); break; in PromoteIntegerResult()
762 ShiftOp = ISD::SRA; in PromoteIntRes_ADDSUBSHLSAT()
844 unsigned ShiftOp = Signed ? ISD::SRA : ISD::SRL; in PromoteIntRes_MULFIX()
952 Res = DAG.getNode(Signed ? ISD::SRA : ISD::SRL, dl, PromotedType, Res, in PromoteIntRes_DIVFIX()
1124 return DAG.getNode(ISD::SRA, SDLoc(N), LHS.getValueType(), LHS, RHS); in PromoteIntRes_SRA()
1491 case ISD::SRA: in PromoteIntegerOperand()
2128 case ISD::SRA: in ExpandIntegerResult()
2270 assert(N->getOpcode() == ISD::SRA && "Unknown shift!"); in ExpandShiftByConstant()
2272 Hi = Lo = DAG.getNode(ISD::SRA, DL, NVT, InH, in ExpandShiftByConstant()
2275 Lo = DAG.getNode(ISD::SRA, DL, NVT, InH, in ExpandShiftByConstant()
[all …]
|
| /external/llvm/lib/Target/MSP430/ |
| D | MSP430ISelLowering.cpp | 91 setOperationAction(ISD::SRA, MVT::i8, Custom); in MSP430TargetLowering()
94 setOperationAction(ISD::SRA, MVT::i16, Custom); in MSP430TargetLowering()
184 case ISD::SRA: return LowerShifts(Op, DAG); in LowerOperation()
728 case ISD::SRA: in LowerShifts()
729 return DAG.getNode(MSP430ISD::SRA, dl, in LowerShifts()
948 SR = DAG.getNode(ISD::SRA, dl, MVT::i16, SR, One); in LowerSETCC()
1130 case MSP430ISD::SRA: return "MSP430ISD::SRA"; in getTargetNodeName()
|