Searched refs:SRHADD (Results 1 – 13 of 13) sorted by relevance
| /external/llvm-project/llvm/lib/Target/AArch64/ |
| D | AArch64ISelLowering.h | 225 SRHADD, enumerator
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| D | AArch64SchedCyclone.td | 414 // SHADD,SHSUB,SRHADD,UHADD,UHSUB,URHADD
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| D | AArch64SchedThunderX3T110.td | 1456 (instregex "^SQADD", "^SQNEG", "^SQSUB", "^SRHADD",
1478 "^SRHADD", "^SUBHNv", "^SUQADD",
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| D | AArch64SchedThunderX2T99.td | 1348 (instregex "^SQADD", "^SQNEG", "^SQSUB", "^SRHADD",
1370 "^SRHADD", "^SUBHNv", "^SUQADD",
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| D | AArch64ISelLowering.cpp | 1784 MAKE_CASE(AArch64ISD::SRHADD) in getTargetNodeName()
3764 IsSignedAdd ? (IsRoundingAdd ? AArch64ISD::SRHADD : AArch64ISD::SHADD) in LowerINTRINSIC_WO_CHAIN()
12343 ? (IsRHADD ? AArch64ISD::SRHADD : AArch64ISD::SHADD) in performVectorTruncateCombine()
12461 (N0Opc == AArch64ISD::URHADD || N0Opc == AArch64ISD::SRHADD || in performConcatVectorsCombine()
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| D | AArch64InstrInfo.td | 553 def AArch64srhadd : SDNode<"AArch64ISD::SRHADD", SDT_AArch64binvec>;
4085 defm SRHADD : SIMDThreeSameVectorBHS<0,0b00010,"srhadd", AArch64srhadd>;
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/ |
| D | AArch64SchedCyclone.td | 413 // SHADD,SHSUB,SRHADD,UHADD,UHSUB,URHADD
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| D | AArch64SchedThunderX2T99.td | 1348 (instregex "^SQADD", "^SQNEG", "^SQSUB", "^SRHADD",
1370 "^SRHADD", "^SUBHNv", "^SUQADD",
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| D | AArch64InstrInfo.td | 3910 defm SRHADD : SIMDThreeSameVectorBHS<0,0b00010,"srhadd",int_aarch64_neon_srhadd>;
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64SchedCyclone.td | 412 // SHADD,SHSUB,SRHADD,UHADD,UHSUB,URHADD
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| D | AArch64InstrInfo.td | 3005 defm SRHADD : SIMDThreeSameVectorBHS<0,0b00010,"srhadd",int_aarch64_neon_srhadd>;
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| /external/llvm-project/llvm/test/CodeGen/AArch64/ |
| D | sve2-intrinsics-uniform-dsp.ll | 890 ; SRHADD
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| /external/vixl/doc/aarch64/ |
| D | supported-instructions-aarch64.md | 5327 ### SRHADD ### subsection
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