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Searched refs:SRI (Results 1 – 25 of 48) sorted by relevance

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/external/llvm/lib/Target/Hexagon/MCTargetDesc/
DHexagonMCChecker.cpp78 for(MCRegAliasIterator SRI(R, &RI, !MCSubRegIterator(R, &RI).isValid()); in init() local
79 SRI.isValid(); in init()
80 ++SRI) in init()
81 if (!MCSubRegIterator(*SRI, &RI).isValid()) in init()
83 Uses.insert(*SRI); in init()
127 for(MCRegAliasIterator SRI(R, &RI, !MCSubRegIterator(R, &RI).isValid()); in init() local
128 SRI.isValid(); in init()
129 ++SRI) { in init()
130 if (MCSubRegIterator(*SRI, &RI).isValid()) in init()
134 if (R == *SRI) { in init()
[all …]
/external/llvm/lib/MC/
DMCRegisterInfo.cpp31 const uint16_t *SRI = SubRegIndices + get(Reg).SubRegIndices; in getSubReg() local
32 for (MCSubRegIterator Subs(Reg, this); Subs.isValid(); ++Subs, ++SRI) in getSubReg()
33 if (*SRI == Idx) in getSubReg()
42 const uint16_t *SRI = SubRegIndices + get(Reg).SubRegIndices; in getSubRegIndex() local
43 for (MCSubRegIterator Subs(Reg, this); Subs.isValid(); ++Subs, ++SRI) in getSubRegIndex()
45 return *SRI; in getSubRegIndex()
/external/llvm-project/llvm/lib/MC/
DMCRegisterInfo.cpp37 const uint16_t *SRI = SubRegIndices + get(Reg).SubRegIndices; in getSubReg() local
38 for (MCSubRegIterator Subs(Reg, this); Subs.isValid(); ++Subs, ++SRI) in getSubReg()
39 if (*SRI == Idx) in getSubReg()
49 const uint16_t *SRI = SubRegIndices + get(Reg).SubRegIndices; in getSubRegIndex() local
50 for (MCSubRegIterator Subs(Reg, this); Subs.isValid(); ++Subs, ++SRI) in getSubRegIndex()
52 return *SRI; in getSubRegIndex()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/MC/
DMCRegisterInfo.cpp37 const uint16_t *SRI = SubRegIndices + get(Reg).SubRegIndices; in getSubReg() local
38 for (MCSubRegIterator Subs(Reg, this); Subs.isValid(); ++Subs, ++SRI) in getSubReg()
39 if (*SRI == Idx) in getSubReg()
49 const uint16_t *SRI = SubRegIndices + get(Reg).SubRegIndices; in getSubRegIndex() local
50 for (MCSubRegIterator Subs(Reg, this); Subs.isValid(); ++Subs, ++SRI) in getSubRegIndex()
52 return *SRI; in getSubRegIndex()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/
DGCNSchedStrategy.cpp34 const SIRegisterInfo *SRI = static_cast<const SIRegisterInfo*>(TRI); in initialize() local
52 SGPRCriticalLimit = SRI->getRegPressureSetLimit(DAG->MF, in initialize()
53 SRI->getSGPRPressureSet()); in initialize()
54 VGPRCriticalLimit = SRI->getRegPressureSetLimit(DAG->MF, in initialize()
55 SRI->getVGPRPressureSet()); in initialize()
64 const SIRegisterInfo *SRI, in initCandidate() argument
86 unsigned NewSGPRPressure = Pressure[SRI->getSGPRPressureSet()]; in initCandidate()
87 unsigned NewVGPRPressure = Pressure[SRI->getVGPRPressureSet()]; in initCandidate()
112 Cand.RPDelta.Excess = PressureChange(SRI->getVGPRPressureSet()); in initCandidate()
117 Cand.RPDelta.Excess = PressureChange(SRI->getSGPRPressureSet()); in initCandidate()
[all …]
DAMDGPUMachineCFGStructurizer.cpp2107 for (auto SRI = PHIInfo.sources_begin(DestReg); SRI != SE; ++SRI) { in prunePHIInfo() local
2108 unsigned SourceReg = (*SRI).first; in prunePHIInfo()
2118 for (auto SRI = PHIInfo.sources_begin(DestReg); SRI != SE; ++SRI) { in prunePHIInfo() local
2119 PHILinearize::PHISourceT Source = *SRI; in prunePHIInfo()
2151 for (auto SRI = PHIInfo.sources_begin(DestReg); SRI != SE; ++SRI) { in createEntryPHI() local
2156 auto SRI = PHIInfo.sources_begin(DestReg); in createEntryPHI() local
2157 unsigned SourceReg = (*SRI).first; in createEntryPHI()
2167 for (auto SRI = PHIInfo.sources_begin(DestReg); SRI != SE; ++SRI) { in createEntryPHI() local
2168 unsigned SourceReg = (*SRI).first; in createEntryPHI()
2170 if (CurrentRegion->contains((*SRI).second)) { in createEntryPHI()
[all …]
DGCNSchedStrategy.h40 const SIRegisterInfo *SRI,
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/MCTargetDesc/
DHexagonMCChecker.cpp79 for (MCRegAliasIterator SRI(R, &RI, !MCSubRegIterator(R, &RI).isValid()); in initReg() local
80 SRI.isValid(); ++SRI) in initReg()
81 if (!MCSubRegIterator(*SRI, &RI).isValid()) in initReg()
83 Uses.insert(*SRI); in initReg()
138 for (MCRegAliasIterator SRI(R, &RI, !MCSubRegIterator(R, &RI).isValid()); in init() local
139 SRI.isValid(); ++SRI) { in init()
140 if (MCSubRegIterator(*SRI, &RI).isValid()) in init()
144 if (R == *SRI) { in init()
153 if (Hexagon::P3_0 != R && Hexagon::P3_0 == *SRI) in init()
158 SoftDefs.insert(*SRI); in init()
[all …]
/external/llvm-project/llvm/lib/Target/Hexagon/MCTargetDesc/
DHexagonMCChecker.cpp79 for (MCRegAliasIterator SRI(R, &RI, !MCSubRegIterator(R, &RI).isValid()); in initReg() local
80 SRI.isValid(); ++SRI) in initReg()
81 if (!MCSubRegIterator(*SRI, &RI).isValid()) in initReg()
83 Uses.insert(*SRI); in initReg()
144 for (MCRegAliasIterator SRI(R, &RI, !MCSubRegIterator(R, &RI).isValid()); in init() local
145 SRI.isValid(); ++SRI) { in init()
146 if (MCSubRegIterator(*SRI, &RI).isValid()) in init()
150 if (R == *SRI) { in init()
159 if (Hexagon::P3_0 != R && Hexagon::P3_0 == *SRI) in init()
164 SoftDefs.insert(*SRI); in init()
[all …]
/external/llvm-project/llvm/lib/Target/WebAssembly/
DWebAssemblyCFGSort.cpp221 SortRegionInfo SRI(MLI, WEI); in sortBlocks() local
224 const SortRegion *R = SRI.getRegionFor(MBB); in sortBlocks()
316 const SortRegion *Region = SRI.getRegionFor(&MBB); in sortBlocks()
342 assert(OnStack.count(SRI.getRegionFor(&MBB)) && in sortBlocks()
345 while (OnStack.size() > 1 && &MBB == SRI.getBottom(OnStack.back())) in sortBlocks()
DWebAssemblyCFGStackify.cpp410 SortRegionInfo SRI(MLI, WEI); in placeLoopMarker() local
419 MachineBasicBlock *Bottom = SRI.getBottom(Loop); in placeLoopMarker()
481 SortRegionInfo SRI(MLI, WEI); in placeTryMarker() local
501 MachineBasicBlock *Bottom = SRI.getBottom(WE); in placeTryMarker()
/external/capstone/
DMCRegisterInfo.c111 const uint16_t *SRI = RI->SubRegIndices + RI->Desc[Reg].SubRegIndices; in MCRegisterInfo_getSubReg() local
117 if (*SRI == Idx) in MCRegisterInfo_getSubReg()
120 ++SRI; in MCRegisterInfo_getSubReg()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/
DCriticalAntiDepBreaker.cpp266 for (MCSubRegIterator SRI(PhysReg, TRI, true); SRI.isValid(); ++SRI) in ScanInstruction() local
267 if (!MO.clobbersPhysReg(*SRI)) in ScanInstruction()
299 for (MCSubRegIterator SRI(Reg, TRI, true); SRI.isValid(); ++SRI) { in ScanInstruction() local
300 unsigned SubregReg = *SRI; in ScanInstruction()
DVirtRegMap.cpp295 LiveInterval::const_iterator &SRI = RangeIterPair.second; in addLiveInsForSubRanges() local
296 while (SRI != SR->end() && SRI->end <= MBBBegin) in addLiveInsForSubRanges()
297 ++SRI; in addLiveInsForSubRanges()
298 if (SRI == SR->end()) in addLiveInsForSubRanges()
300 if (SRI->start <= MBBBegin) in addLiveInsForSubRanges()
/external/llvm-project/llvm/lib/CodeGen/
DCriticalAntiDepBreaker.cpp263 for (MCSubRegIterator SRI(PhysReg, TRI, true); SRI.isValid(); ++SRI) in ScanInstruction() local
264 if (!MO.clobbersPhysReg(*SRI)) in ScanInstruction()
296 for (MCSubRegIterator SRI(Reg, TRI, true); SRI.isValid(); ++SRI) { in ScanInstruction() local
297 unsigned SubregReg = *SRI; in ScanInstruction()
DVirtRegMap.cpp295 LiveInterval::const_iterator &SRI = RangeIterPair.second; in addLiveInsForSubRanges() local
296 while (SRI != SR->end() && SRI->end <= MBBBegin) in addLiveInsForSubRanges()
297 ++SRI; in addLiveInsForSubRanges()
298 if (SRI == SR->end()) in addLiveInsForSubRanges()
300 if (SRI->start <= MBBBegin) in addLiveInsForSubRanges()
/external/llvm/lib/CodeGen/
DVirtRegMap.cpp272 LiveInterval::const_iterator &SRI = RangeIterPair.second; in addLiveInsForSubRanges() local
273 while (SRI != SR->end() && SRI->end <= MBBBegin) in addLiveInsForSubRanges()
274 ++SRI; in addLiveInsForSubRanges()
275 if (SRI == SR->end()) in addLiveInsForSubRanges()
277 if (SRI->start <= MBBBegin) in addLiveInsForSubRanges()
DCriticalAntiDepBreaker.cpp273 for (MCSubRegIterator SRI(Reg, TRI, true); SRI.isValid(); ++SRI) { in ScanInstruction() local
274 unsigned SubregReg = *SRI; in ScanInstruction()
/external/llvm-project/llvm/lib/Target/AMDGPU/
DGCNSchedStrategy.cpp34 const SIRegisterInfo *SRI = static_cast<const SIRegisterInfo*>(TRI); in initialize() local
52 SGPRCriticalLimit = SRI->getRegPressureSetLimit(DAG->MF, in initialize()
54 VGPRCriticalLimit = SRI->getRegPressureSetLimit(DAG->MF, in initialize()
64 const SIRegisterInfo *SRI, in initCandidate() argument
148 const SIRegisterInfo *SRI = static_cast<const SIRegisterInfo*>(TRI); in pickNodeFromQueue() local
156 initCandidate(TryCand, SU, Zone.isTop(), RPTracker, SRI, in pickNodeFromQueue()
DAMDGPUMachineCFGStructurizer.cpp2108 for (auto SRI = PHIInfo.sources_begin(DestReg); SRI != SE; ++SRI) { in prunePHIInfo() local
2109 unsigned SourceReg = (*SRI).first; in prunePHIInfo()
2119 for (auto SRI = PHIInfo.sources_begin(DestReg); SRI != SE; ++SRI) { in prunePHIInfo() local
2120 PHILinearize::PHISourceT Source = *SRI; in prunePHIInfo()
2152 for (auto SRI = PHIInfo.sources_begin(DestReg); SRI != SE; ++SRI) { in createEntryPHI() local
2157 auto SRI = PHIInfo.sources_begin(DestReg); in createEntryPHI() local
2158 unsigned SourceReg = (*SRI).first; in createEntryPHI()
2168 for (auto SRI = PHIInfo.sources_begin(DestReg); SRI != SE; ++SRI) { in createEntryPHI() local
2169 unsigned SourceReg = (*SRI).first; in createEntryPHI()
2171 if (CurrentRegion->contains((*SRI).second)) { in createEntryPHI()
[all …]
DGCNSchedStrategy.h40 const SIRegisterInfo *SRI,
/external/llvm-project/llvm/utils/TableGen/
DCodeGenRegisters.cpp137 for (CodeGenSubRegIndex *SRI : SubIdx->ConcatenationOf) in computeConcatTransitiveClosure()
138 assert(SRI->ConcatenationOf.empty() && "No transitive closure?"); in computeConcatTransitiveClosure()
319 SubRegMap::const_iterator SRI = Map.find(I->first); in computeSubRegs() local
320 if (SRI == Map.end()) in computeSubRegs()
324 if (SubRegs.count(I->second) || !Orphans.erase(SRI->second)) in computeSubRegs()
327 SubRegs.insert(std::make_pair(I->second, SRI->second)); in computeSubRegs()
1165 for (CodeGenSubRegIndex &SRI : SubRegIndices) { in CodeGenRegBank()
1166 SRI.computeConcatTransitiveClosure(); in CodeGenRegBank()
1167 if (!SRI.ConcatenationOf.empty()) in CodeGenRegBank()
1169 SmallVector<CodeGenSubRegIndex*,8>(SRI.ConcatenationOf.begin(), in CodeGenRegBank()
[all …]
DRegisterInfoEmitter.cpp1677 for (const CodeGenSubRegIndex &SRI : RegBank.getSubRegIndices()) { in debugDump() local
1678 OS << "SubRegIndex " << SRI.getName() << ":\n"; in debugDump()
1679 OS << "\tLaneMask: " << PrintLaneMask(SRI.LaneMask) << '\n'; in debugDump()
1680 OS << "\tAllSuperRegsCovered: " << SRI.AllSuperRegsCovered << '\n'; in debugDump()
/external/llvm/utils/TableGen/
DCodeGenRegisters.cpp267 SubRegMap::const_iterator SRI = Map.find(I->first); in computeSubRegs() local
268 if (SRI == Map.end()) in computeSubRegs()
272 if (SubRegs.count(I->second) || !Orphans.erase(SRI->second)) in computeSubRegs()
275 SubRegs.insert(std::make_pair(I->second, SRI->second)); in computeSubRegs()
1449 for (CodeGenRegister::SubRegMap::const_iterator SRI = SRM.begin(), in normalizeWeight() local
1450 SRE = SRM.end(); SRI != SRE; ++SRI) { in normalizeWeight()
1451 if (SRI->second == Reg) in normalizeWeight()
1454 Changed |= normalizeWeight(SRI->second, UberSets, RegSets, in normalizeWeight()
/external/llvm-project/llvm/lib/CodeGen/LiveDebugValues/
DInstrRefBasedImpl.cpp1812 for (MCSuperRegIterator SRI(DstRegNum, TRI); SRI.isValid(); ++SRI) in performCopy() local
1813 MTracker->defReg(*SRI, CurBB, CurInst); in performCopy()
1827 for (MCSubRegIndexIterator SRI(SrcRegNum, TRI); SRI.isValid(); ++SRI) { in performCopy() local
1828 unsigned SrcSubReg = SRI.getSubReg(); in performCopy()
1829 unsigned SubRegIdx = SRI.getSubRegIndex(); in performCopy()

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