Home
last modified time | relevance | path

Searched refs:SRL (Results 1 – 25 of 302) sorted by relevance

12345678910>>...13

/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Lanai/
DLanaiAluCode.h36 SRL = 0x27, enumerator
94 case SRL: in lanaiAluCodeToString()
113 .Case("srl", SRL) in stringToLanaiAluCode()
136 case ISD::SRL: in isdToLanaiAluCode()
137 return AluCode::SRL; in isdToLanaiAluCode()
/external/llvm-project/llvm/lib/Target/Lanai/
DLanaiAluCode.h36 SRL = 0x27, enumerator
94 case SRL: in lanaiAluCodeToString()
113 .Case("srl", SRL) in stringToLanaiAluCode()
136 case ISD::SRL: in isdToLanaiAluCode()
137 return AluCode::SRL; in isdToLanaiAluCode()
/external/llvm/lib/Target/Lanai/
DLanaiAluCode.h37 SRL = 0x27, enumerator
95 case SRL: in lanaiAluCodeToString()
114 .Case("srl", SRL) in stringToLanaiAluCode()
137 case ISD::SRL: in isdToLanaiAluCode()
138 return AluCode::SRL; in isdToLanaiAluCode()
/external/llvm/lib/Target/X86/
DX86TargetTransformInfo.cpp136 { ISD::SRL, MVT::v16i32, 1 }, in getArithmeticInstrCost()
139 { ISD::SRL, MVT::v8i64, 1 }, in getArithmeticInstrCost()
152 { ISD::SRL, MVT::v4i32, 1 }, in getArithmeticInstrCost()
155 { ISD::SRL, MVT::v8i32, 1 }, in getArithmeticInstrCost()
158 { ISD::SRL, MVT::v2i64, 1 }, in getArithmeticInstrCost()
160 { ISD::SRL, MVT::v4i64, 1 }, in getArithmeticInstrCost()
179 { ISD::SRL, MVT::v16i8, 2 }, in getArithmeticInstrCost()
182 { ISD::SRL, MVT::v8i16, 2 }, in getArithmeticInstrCost()
185 { ISD::SRL, MVT::v4i32, 2 }, in getArithmeticInstrCost()
188 { ISD::SRL, MVT::v2i64, 2 }, in getArithmeticInstrCost()
[all …]
/external/python/cpython2/Modules/_ctypes/libffi/src/mips/
Dn32.S120 SRL t4, t6, 1*FFI_FLAG_BITS
131 SRL t4, t6, 2*FFI_FLAG_BITS
142 SRL t4, t6, 3*FFI_FLAG_BITS
153 SRL t4, t6, 4*FFI_FLAG_BITS
164 SRL t4, t6, 5*FFI_FLAG_BITS
175 SRL t4, t6, 6*FFI_FLAG_BITS
186 SRL t4, t6, 7*FFI_FLAG_BITS
206 SRL t6, 8*FFI_FLAG_BITS
Dffitarget.h152 # define SRL srl macro
159 # define SRL dsrl macro
/external/libffi/src/mips/
Dffitarget.h152 # define SRL srl macro
159 # define SRL dsrl macro
Dn32.S137 SRL t4, t6, 1*FFI_FLAG_BITS
148 SRL t4, t6, 2*FFI_FLAG_BITS
159 SRL t4, t6, 3*FFI_FLAG_BITS
170 SRL t4, t6, 4*FFI_FLAG_BITS
181 SRL t4, t6, 5*FFI_FLAG_BITS
192 SRL t4, t6, 6*FFI_FLAG_BITS
203 SRL t4, t6, 7*FFI_FLAG_BITS
227 SRL t6, 8*FFI_FLAG_BITS
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/
DX86TargetTransformInfo.cpp292 { ISD::SRL, MVT::v64i8, 2 }, // psrlw + pand. in getArithmeticInstrCost()
318 { ISD::SRL, MVT::v32i8, 2 }, // psrlw + pand. in getArithmeticInstrCost()
333 { ISD::SRL, MVT::v16i8, 2 }, // psrlw + pand. in getArithmeticInstrCost()
337 { ISD::SRL, MVT::v32i8, 4+2 }, // 2*(psrlw + pand) + split. in getArithmeticInstrCost()
452 { ISD::SRL, MVT::v16i16, 1 }, // psrlw. in getArithmeticInstrCost()
470 { ISD::SRL, MVT::v8i16, 1 }, // psrlw. in getArithmeticInstrCost()
471 { ISD::SRL, MVT::v4i32, 1 }, // psrld. in getArithmeticInstrCost()
472 { ISD::SRL, MVT::v2i64, 1 }, // psrlq. in getArithmeticInstrCost()
499 { ISD::SRL, MVT::v8i16, 1 }, // vpsrlvw in getArithmeticInstrCost()
503 { ISD::SRL, MVT::v16i16, 1 }, // vpsrlvw in getArithmeticInstrCost()
[all …]
/external/llvm-project/llvm/test/CodeGen/Mips/
Dfcopysign-f32-f64.ll45 ; 64: srl $[[SRL:[0-9]+]], $[[MFC:[0-9]+]], 31
46 ; 64: dsll $[[DSLL:[0-9]+]], $[[SRL]], 63
/external/llvm/test/CodeGen/Mips/
Dfcopysign-f32-f64.ll40 ; 64-DAG: srl $[[SRL:[0-9]+]], $[[MFC:[0-9]+]], 31
41 ; 64: dsll $[[DSLL:[0-9]+]], $[[SRL]], 63
/external/llvm/test/CodeGen/SystemZ/
Dshift-09.ll25 ; Check that we use SRLK over SRL where useful.
35 ; Check that we use SRL over SRLK where possible.
Dshift-02.ll5 ; Check the low end of the SRL range.
14 ; Check the high end of the defined SRL range.
/external/llvm-project/llvm/test/CodeGen/SystemZ/
Dshift-09.ll28 ; Check that we use SRLK over SRL where useful.
39 ; Check that we use SRL over SRLK where possible.
Dshift-02.ll6 ; Check the low end of the SRL range.
16 ; Check the high end of the defined SRL range.
/external/llvm-project/llvm/lib/Target/X86/
DX86TargetTransformInfo.cpp305 { ISD::SRL, MVT::v64i8, 2 }, // psrlw + pand. in getArithmeticInstrCost()
322 { ISD::SRL, MVT::v64i8, 4 }, // psrlw + pand. in getArithmeticInstrCost()
340 { ISD::SRL, MVT::v32i8, 2 }, // psrlw + pand. in getArithmeticInstrCost()
360 { ISD::SRL, MVT::v16i8, 2 }, // psrlw + pand. in getArithmeticInstrCost()
364 { ISD::SRL, MVT::v32i8, 4+2 }, // 2*(psrlw + pand) + split. in getArithmeticInstrCost()
495 { ISD::SRL, MVT::v8i16, 1 }, // vpsrlvw in getArithmeticInstrCost()
499 { ISD::SRL, MVT::v16i16, 1 }, // vpsrlvw in getArithmeticInstrCost()
503 { ISD::SRL, MVT::v32i16, 1 }, // vpsrlvw in getArithmeticInstrCost()
514 { ISD::SRL, MVT::v16i16, 1 }, // psrlw. in getArithmeticInstrCost()
517 { ISD::SRL, MVT::v32i16, 2 }, // 2*psrlw. in getArithmeticInstrCost()
[all …]
/external/llvm/lib/CodeGen/SelectionDAG/
DLegalizeIntegerTypes.cpp87 case ISD::SRL: Res = PromoteIntRes_SRL(N); break; in PromoteIntegerResult()
320 ISD::SRL, dl, NVT, DAG.getNode(ISD::BSWAP, dl, NVT, Op), in PromoteIntRes_BSWAP()
333 ISD::SRL, dl, NVT, DAG.getNode(ISD::BITREVERSE, dl, NVT, Op), in PromoteIntRes_BITREVERSE()
689 return DAG.getNode(ISD::SRL, SDLoc(N), LHS.getValueType(), LHS, RHS); in PromoteIntRes_SRL()
788 SDValue Hi = DAG.getNode(ISD::SRL, DL, Mul.getValueType(), Mul, in PromoteIntRes_XMULO()
920 case ISD::SRL: in PromoteIntegerOperand()
1395 case ISD::SRL: ExpandIntRes_Shift(N, Lo, Hi); break; in ExpandIntegerResult()
1457 DAG.getNode(ISD::SRL, DL, NVT, InL, in ExpandShiftByConstant()
1463 if (N->getOpcode() == ISD::SRL) { in ExpandShiftByConstant()
1467 Lo = DAG.getNode(ISD::SRL, DL, in ExpandShiftByConstant()
[all …]
DTargetLowering.cpp671 if (InOp.getOpcode() == ISD::SRL && in SimplifyDemandedBits()
679 Opc = ISD::SRL; in SimplifyDemandedBits()
719 InnerOp.getOpcode() == ISD::SRL && in SimplifyDemandedBits()
746 case ISD::SRL: in SimplifyDemandedBits()
771 unsigned Opc = ISD::SRL; in SimplifyDemandedBits()
804 TLO.DAG.getNode(ISD::SRL, dl, Op.getValueType(), in SimplifyDemandedBits()
844 TLO.DAG.getNode(ISD::SRL, dl, VT, Op.getOperand(0), in SimplifyDemandedBits()
854 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL, dl, VT, in SimplifyDemandedBits()
1052 case ISD::SRL: in SimplifyDemandedBits()
1056 !isTypeDesirableForOp(ISD::SRL, Op.getValueType())) in SimplifyDemandedBits()
[all …]
/external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/SelectionDAG/
DLegalizeIntegerTypes.cpp90 case ISD::SRL: Res = PromoteIntRes_SRL(N); break; in PromoteIntegerResult()
355 Res = DAG.getNode(ISD::SRL, dl, NOutVT, Res, in PromoteIntRes_BITCAST()
407 return DAG.getNode(ISD::SRL, dl, NVT, DAG.getNode(ISD::BSWAP, dl, NVT, Op), in PromoteIntRes_BSWAP()
419 return DAG.getNode(ISD::SRL, dl, NVT, in PromoteIntRes_BITREVERSE()
700 ShiftOp = ISD::SRL; in PromoteIntRes_ADDSUBSAT()
776 unsigned ShiftOp = Signed ? ISD::SRA : ISD::SRL; in PromoteIntRes_MULFIX()
999 return DAG.getNode(ISD::SRL, SDLoc(N), LHS.getValueType(), LHS, RHS); in PromoteIntRes_SRL()
1157 SDValue Hi = DAG.getNode(ISD::SRL, DL, Mul.getValueType(), Mul, in PromoteIntRes_XMULO()
1292 case ISD::SRL: in PromoteIntegerOperand()
1897 case ISD::SRL: ExpandIntRes_Shift(N, Lo, Hi); break; in ExpandIntegerResult()
[all …]
/external/llvm-project/llvm/test/MC/Mips/mips1/
Dvalid.s147 # CHECK-NEXT: # <MCInst #{{[0-9]+}} SRL
150 # CHECK-NEXT: # <MCInst #{{[0-9]+}} SRL
153 # CHECK-NEXT: # <MCInst #{{[0-9]+}} SRL
156 # CHECK-NEXT: # <MCInst #{{[0-9]+}} SRL
/external/llvm-project/llvm/lib/CodeGen/SelectionDAG/
DLegalizeIntegerTypes.cpp91 case ISD::SRL: Res = PromoteIntRes_SRL(N); break; in PromoteIntegerResult()
399 Res = DAG.getNode(ISD::SRL, dl, NOutVT, Res, in PromoteIntRes_BITCAST()
456 return DAG.getNode(ISD::SRL, dl, NVT, DAG.getNode(ISD::BSWAP, dl, NVT, Op), in PromoteIntRes_BSWAP()
468 return DAG.getNode(ISD::SRL, dl, NVT, in PromoteIntRes_BITREVERSE()
767 ShiftOp = ISD::SRL; in PromoteIntRes_ADDSUBSHLSAT()
844 unsigned ShiftOp = Signed ? ISD::SRA : ISD::SRL; in PromoteIntRes_MULFIX()
952 Res = DAG.getNode(Signed ? ISD::SRA : ISD::SRL, dl, PromotedType, Res, in PromoteIntRes_DIVFIX()
1133 return DAG.getNode(ISD::SRL, SDLoc(N), LHS.getValueType(), LHS, RHS); in PromoteIntRes_SRL()
1172 Res = DAG.getNode(IsFSHR ? ISD::SRL : ISD::SHL, DL, VT, Res, Amount); in PromoteIntRes_FunnelShift()
1174 Res = DAG.getNode(ISD::SRL, DL, VT, Res, HiShift); in PromoteIntRes_FunnelShift()
[all …]
DTargetLowering.cpp1451 if (Op0.getOpcode() == ISD::SRL) { in SimplifyDemandedBits()
1460 Opc = ISD::SRL; in SimplifyDemandedBits()
1494 if (Op0.hasOneUse() && InnerOp.getOpcode() == ISD::SRL && in SimplifyDemandedBits()
1544 case ISD::SRL: { in SimplifyDemandedBits()
1564 unsigned Opc = ISD::SRL; in SimplifyDemandedBits()
1613 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL, dl, VT, Op0, Op1)); in SimplifyDemandedBits()
1647 Op, TLO.DAG.getNode(ISD::SRL, dl, VT, Op0, Op1, Flags)); in SimplifyDemandedBits()
1654 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL, dl, VT, Op0, NewSA)); in SimplifyDemandedBits()
1991 case ISD::SRL: in SimplifyDemandedBits()
1994 if (TLO.LegalTypes() && !isTypeDesirableForOp(ISD::SRL, VT)) in SimplifyDemandedBits()
[all …]
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/
DARMSelectionDAGInfo.h27 case ISD::SRL: return ARM_AM::lsr; in getShiftOpcForNode()
/external/llvm-project/llvm/lib/Target/ARM/
DARMSelectionDAGInfo.h27 case ISD::SRL: return ARM_AM::lsr; in getShiftOpcForNode()
/external/llvm/lib/Target/ARM/
DARMSelectionDAGInfo.h28 case ISD::SRL: return ARM_AM::lsr; in getShiftOpcForNode()

12345678910>>...13