| /external/llvm-project/llvm/lib/Transforms/Utils/ |
| D | IntegerDivision.cpp | 65 Value *SRem = Builder.CreateSub(Xored, DividendSign); in generateSignedRemainderCode() local
70 return SRem; in generateSignedRemainderCode()
376 assert((Rem->getOpcode() == Instruction::SRem || in expandRemainder()
388 if (Rem->getOpcode() == Instruction::SRem) { in expandRemainder()
486 assert((Rem->getOpcode() == Instruction::SRem || in expandRemainderUpTo32Bits()
511 if (Rem->getOpcode() == Instruction::SRem) { in expandRemainderUpTo32Bits()
535 assert((Rem->getOpcode() == Instruction::SRem || in expandRemainderUpTo64Bits()
559 if (Rem->getOpcode() == Instruction::SRem) { in expandRemainderUpTo64Bits()
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| D | BypassSlowDivision.cpp | 94 SlowDivOrRem->getOpcode() == Instruction::SRem; in isSignedOp()
118 case Instruction::SRem: in FastDivInsertionTask()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Transforms/Utils/ |
| D | IntegerDivision.cpp | 65 Value *SRem = Builder.CreateSub(Xored, DividendSign); in generateSignedRemainderCode() local
70 return SRem; in generateSignedRemainderCode()
376 assert((Rem->getOpcode() == Instruction::SRem || in expandRemainder()
388 if (Rem->getOpcode() == Instruction::SRem) { in expandRemainder()
486 assert((Rem->getOpcode() == Instruction::SRem || in expandRemainderUpTo32Bits()
511 if (Rem->getOpcode() == Instruction::SRem) { in expandRemainderUpTo32Bits()
535 assert((Rem->getOpcode() == Instruction::SRem || in expandRemainderUpTo64Bits()
559 if (Rem->getOpcode() == Instruction::SRem) { in expandRemainderUpTo64Bits()
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| D | BypassSlowDivision.cpp | 94 SlowDivOrRem->getOpcode() == Instruction::SRem; in isSignedOp()
118 case Instruction::SRem: in FastDivInsertionTask()
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| /external/llvm/lib/Transforms/Utils/ |
| D | IntegerDivision.cpp | 66 Value *SRem = Builder.CreateSub(Xored, DividendSign); in generateSignedRemainderCode() local
71 return SRem; in generateSignedRemainderCode()
377 assert((Rem->getOpcode() == Instruction::SRem || in expandRemainder()
389 if (Rem->getOpcode() == Instruction::SRem) { in expandRemainder()
487 assert((Rem->getOpcode() == Instruction::SRem || in expandRemainderUpTo32Bits()
512 if (Rem->getOpcode() == Instruction::SRem) { in expandRemainderUpTo32Bits()
536 assert((Rem->getOpcode() == Instruction::SRem || in expandRemainderUpTo64Bits()
560 if (Rem->getOpcode() == Instruction::SRem) { in expandRemainderUpTo64Bits()
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| D | BypassSlowDivision.cpp | 223 bool UseRemOp = Opcode == Instruction::SRem || Opcode == Instruction::URem; in bypassSlowDivision()
225 Opcode == Instruction::SRem; in bypassSlowDivision()
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| /external/llvm-project/mlir/test/Dialect/SPIRV/ |
| D | arithmetic-ops.mlir | 189 // spv.SRem
193 // CHECK: spv.SRem
194 %0 = spv.SRem %arg, %arg : i32
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| /external/llvm-project/polly/lib/Support/ |
| D | SCEVValidator.cpp | 420 ValidatorResult visitSRemInstruction(Instruction *SRem, const SCEV *S) { in visitSRemInstruction()
421 assert(SRem->getOpcode() == Instruction::SRem && in visitSRemInstruction()
424 auto *Divisor = SRem->getOperand(1); in visitSRemInstruction()
427 return visitGenericInst(SRem, S); in visitSRemInstruction()
429 auto *Dividend = SRem->getOperand(0); in visitSRemInstruction()
455 case Instruction::SRem: in visitUnknown()
595 if (!Inst || (Inst->getOpcode() != Instruction::SRem && in follow()
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| D | SCEVAffinator.cpp | 523 PWACtx SCEVAffinator::visitSRemInstruction(Instruction *SRem) { in visitSRemInstruction() argument
524 assert(SRem->getOpcode() == Instruction::SRem && "Assumed SRem instruction!"); in visitSRemInstruction()
527 auto *Divisor = SRem->getOperand(1); in visitSRemInstruction()
533 auto *Dividend = SRem->getOperand(0); in visitSRemInstruction()
547 case Instruction::SRem: in visitUnknown()
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| /external/llvm-project/mlir/test/Dialect/SPIRV/Serialization/ |
| D | arithmetic-ops.mlir | 80 // CHECK: {{%.*}} = spv.SRem {{%.*}}, {{%.*}} : vector<4xi32>
81 %0 = spv.SRem %arg0, %arg1 : vector<4xi32>
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| /external/llvm-project/mlir/test/Conversion/SPIRVToLLVM/ |
| D | arithmetic-ops-to-llvm.mlir | 220 // spv.SRem
226 %0 = spv.SRem %arg0, %arg1 : i32
233 %0 = spv.SRem %arg0, %arg1 : vector<4xi32>
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| /external/llvm-project/llvm/unittests/Transforms/Utils/ |
| D | IntegerDivisionTest.cpp | 82 TEST(IntegerDivision, SRem) { in TEST() argument
101 EXPECT_TRUE(BB->front().getOpcode() == Instruction::SRem); in TEST()
222 EXPECT_TRUE(BB->front().getOpcode() == Instruction::SRem); in TEST()
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| /external/llvm/unittests/Transforms/Utils/ |
| D | IntegerDivision.cpp | 83 TEST(IntegerDivision, SRem) { in TEST() argument
102 EXPECT_TRUE(BB->front().getOpcode() == Instruction::SRem); in TEST()
223 EXPECT_TRUE(BB->front().getOpcode() == Instruction::SRem); in TEST()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Transforms/Scalar/ |
| D | DivRemPairs.cpp | 106 case Instruction::SRem: in isRemExpanded()
134 else if (I.getOpcode() == Instruction::SRem) in getWorklist()
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| /external/llvm-project/llvm/lib/Transforms/Scalar/ |
| D | DivRemPairs.cpp | 108 case Instruction::SRem: in isRemExpanded()
137 else if (I.getOpcode() == Instruction::SRem) in getWorklist()
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| D | CorrelatedValuePropagation.cpp | 622 Instr->getOpcode() == Instruction::SRem); in narrowSDivOrSRem()
717 assert(SDI->getOpcode() == Instruction::SRem); in processSRem()
826 Instr->getOpcode() == Instruction::SRem); in processSDivOrSRem()
834 if (Instr->getOpcode() == Instruction::SRem) in processSDivOrSRem()
998 case Instruction::SRem: in runImpl()
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| /external/llvm-project/llvm/lib/Target/AMDGPU/ |
| D | AMDGPUCodeGenPrepare.cpp | 270 I.getOpcode() == Instruction::SDiv || I.getOpcode() == Instruction::SRem; in isSigned()
341 I.getOpcode() == Instruction::SRem || in promoteUniformOpToI32()
1035 Opc == Instruction::SRem || Opc == Instruction::SDiv); in expandDivRem32()
1045 bool IsSigned = Opc == Instruction::SRem || Opc == Instruction::SDiv; in expandDivRem32()
1164 bool IsSigned = Opc == Instruction::SDiv || Opc == Instruction::SRem; in shrinkDivRem64()
1194 if (Opc == Instruction::URem || Opc == Instruction::SRem) { in expandDivRem64()
1222 Opc == Instruction::SRem || Opc == Instruction::SDiv) && in visitBinaryOperator()
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| /external/llvm-project/polly/include/polly/Support/ |
| D | SCEVAffinator.h | 116 PWACtx visitSRemInstruction(llvm::Instruction *SRem);
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
| D | AMDGPUCodeGenPrepare.cpp | 222 I.getOpcode() == Instruction::SDiv || I.getOpcode() == Instruction::SRem; in isSigned()
291 I.getOpcode() == Instruction::SRem || in promoteUniformOpToI32()
745 Opc == Instruction::SRem || Opc == Instruction::SDiv); in expandDivRem32()
755 bool IsSigned = Opc == Instruction::SRem || Opc == Instruction::SDiv; in expandDivRem32()
899 Opc == Instruction::SRem || Opc == Instruction::SDiv) && in visitBinaryOperator()
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| /external/llvm-project/llvm/include/llvm/Transforms/InstCombine/ |
| D | InstCombiner.h | 304 case Instruction::SRem: // X % 1 = 0 in getSafeVectorConstantForBinop()
322 case Instruction::SRem: // 0 % X = 0 in getSafeVectorConstantForBinop()
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| /external/llvm/lib/Target/SystemZ/ |
| D | SystemZTargetTransformInfo.cpp | 166 case Instruction::SRem: in getIntImmCost()
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| /external/llvm-project/llvm/lib/FuzzMutate/ |
| D | Operations.cpp | 24 Ops.push_back(binOpDescriptor(1, Instruction::SRem)); in describeFuzzerIntOps()
102 case Instruction::SRem: in binOpDescriptor()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/FuzzMutate/ |
| D | Operations.cpp | 24 Ops.push_back(binOpDescriptor(1, Instruction::SRem)); in describeFuzzerIntOps()
102 case Instruction::SRem: in binOpDescriptor()
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| /external/llvm-project/mlir/include/mlir/Dialect/SPIRV/ |
| D | SPIRVArithmeticOps.td | 480 def SPV_SRemOp : SPV_ArithmeticBinaryOp<"SRem", SPV_Integer, []> {
502 srem-op ::= ssa-id `=` `spv.SRem` ssa-use, ssa-use
508 %4 = spv.SRem %0, %1 : i32
509 %5 = spv.SRem %2, %3 : vector<4xi32>
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| /external/swiftshader/third_party/subzero/pnacl-llvm/ |
| D | NaClBitcodeDecoders.cpp | 94 LLVMOpcode = Ty->isFPOrFPVectorTy() ? Instruction::FRem : Instruction::SRem; in DecodeBinaryOpcode()
|