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Searched refs:SSHLSAT (Results 1 – 14 of 14) sorted by relevance

/external/llvm-project/llvm/test/CodeGen/AMDGPU/GlobalISel/
Dcombine-shift-of-shifted-logic-shlsat.mir218 ; CHECK: [[SSHLSAT:%[0-9]+]]:_(s32) = G_SSHLSAT [[COPY]], [[C2]](s32)
220 ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[SSHLSAT]], [[SSHLSAT1]]
246 ; CHECK: [[SSHLSAT:%[0-9]+]]:_(s32) = G_SSHLSAT [[COPY]], [[C2]](s32)
248 ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[SSHLSAT]], [[SSHLSAT1]]
275 ; CHECK: [[SSHLSAT:%[0-9]+]]:_(s32) = G_SSHLSAT [[COPY]], [[C2]](s32)
277 ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[SSHLSAT]], [[SSHLSAT1]]
304 ; CHECK: [[SSHLSAT:%[0-9]+]]:_(s32) = G_SSHLSAT [[COPY]], [[C2]](s32)
306 ; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[SSHLSAT]], [[SSHLSAT1]]
332 ; CHECK: [[SSHLSAT:%[0-9]+]]:_(s32) = G_SSHLSAT [[COPY]], [[C2]](s32)
334 ; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[SSHLSAT]], [[SSHLSAT1]]
[all …]
Dcombine-shift-imm-chain-shlsat.mir15 ; CHECK: [[SSHLSAT:%[0-9]+]]:_(s32) = G_SSHLSAT [[COPY]], [[C]](s32)
16 ; CHECK: $vgpr0 = COPY [[SSHLSAT]](s32)
37 ; CHECK: [[SSHLSAT:%[0-9]+]]:_(s32) = G_SSHLSAT [[COPY]], [[C]](s32)
38 …; CHECK: [[INT:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.readfirstlane), [[SSHLSAT]](s…
66 ; CHECK: [[SSHLSAT:%[0-9]+]]:_(s32) = G_SSHLSAT [[COPY]], [[C]](s32)
67 ; CHECK: $vgpr0 = COPY [[SSHLSAT]](s32)
92 ; CHECK: [[SSHLSAT:%[0-9]+]]:_(s64) = G_SSHLSAT [[MV]], [[C]](s64)
93 ; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[SSHLSAT]](s64)
Dirtranslator-sat.ll408 ; CHECK: [[SSHLSAT:%[0-9]+]]:_(s16) = G_SSHLSAT [[TRUNC]], [[TRUNC1]](s16)
409 ; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[SSHLSAT]](s16)
425 ; CHECK: [[SSHLSAT:%[0-9]+]]:_(s32) = G_SSHLSAT [[COPY]], [[COPY1]](s32)
426 ; CHECK: $vgpr0 = COPY [[SSHLSAT]](s32)
445 ; CHECK: [[SSHLSAT:%[0-9]+]]:_(s64) = G_SSHLSAT [[MV]], [[MV1]](s64)
446 ; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[SSHLSAT]](s64)
467 …; CHECK: [[SSHLSAT:%[0-9]+]]:_(<2 x s32>) = G_SSHLSAT [[BUILD_VECTOR]], [[BUILD_VECTOR1]](<2 x s…
468 ; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[SSHLSAT]](<2 x s32>)
Dcombine-shift-imm-chain-illegal-types.mir215 ; CHECK: [[SSHLSAT:%[0-9]+]]:_(s44) = G_SSHLSAT [[TRUNC]], [[C]](s44)
216 ; CHECK: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[SSHLSAT]](s44)
253 ; CHECK: [[SSHLSAT:%[0-9]+]]:_(s55) = G_SSHLSAT [[TRUNC]], [[C]](s55)
254 ; CHECK: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[SSHLSAT]](s55)
/external/llvm-project/llvm/include/llvm/CodeGen/
DISDOpcodes.h339 SSHLSAT, enumerator
/external/llvm-project/llvm/lib/CodeGen/SelectionDAG/
DSelectionDAGDumper.cpp315 case ISD::SSHLSAT: return "sshlsat"; in getOperationName()
DLegalizeVectorOps.cpp456 case ISD::SSHLSAT: in LegalizeOp()
DLegalizeIntegerTypes.cpp162 case ISD::SSHLSAT: in PromoteIntegerResult()
738 bool IsShift = Opcode == ISD::USHLSAT || Opcode == ISD::SSHLSAT; in PromoteIntRes_ADDSUBSHLSAT()
761 case ISD::SSHLSAT: in PromoteIntRes_ADDSUBSHLSAT()
2143 case ISD::SSHLSAT: in ExpandIntegerResult()
DLegalizeVectorTypes.cpp132 case ISD::SSHLSAT: in ScalarizeVectorResult()
1000 case ISD::SSHLSAT: in SplitVectorResult()
2891 case ISD::SSHLSAT: in WidenVectorResult()
DLegalizeDAG.cpp1138 case ISD::SSHLSAT: in LegalizeOp()
3549 case ISD::SSHLSAT: in ExpandNode()
DTargetLowering.cpp7624 bool IsSigned = Opcode == ISD::SSHLSAT; in expandShlSat()
7630 assert((Node->getOpcode() == ISD::SSHLSAT || in expandShlSat()
DSelectionDAGBuilder.cpp6275 setValue(&I, DAG.getNode(ISD::SSHLSAT, sdl, Op1.getValueType(), Op1, Op2)); in visitIntrinsicCall()
/external/llvm-project/llvm/lib/CodeGen/
DTargetLoweringBase.cpp767 setOperationAction(ISD::SSHLSAT, VT, Expand); in initActions()
/external/llvm-project/llvm/include/llvm/Target/
DTargetSelectionDAG.td401 def sshlsat : SDNode<"ISD::SSHLSAT" , SDTIntBinOp>;