| /external/vixl/src/aarch64/ |
| D | cpu-features-auditor-aarch64.cc | 564 case STLLRB: in VisitLoadStoreExclusive()
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| D | constants-aarch64.h | 1233 STLLRB = LoadStoreExclusiveFixed | 0x00800000, enumerator
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| D | disasm-aarch64.cc | 1466 V(STLLRB, "stllrb", "'Wt") \
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| D | assembler-aarch64.cc | 1601 Emit(STLLRB | Rs_mask | Rt(rt) | Rt2_mask | RnSP(dst.GetBaseRegister())); in stllrb()
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| D | simulator-aarch64.cc | 2748 case STLLRB: in VisitLoadStoreExclusive()
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| /external/llvm/lib/Target/AArch64/Disassembler/ |
| D | AArch64Disassembler.cpp | 1114 case AArch64::STLLRB: in DecodeExclusiveLdStInstruction()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/Disassembler/ |
| D | AArch64Disassembler.cpp | 1320 case AArch64::STLLRB: in DecodeExclusiveLdStInstruction()
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| /external/llvm-project/llvm/lib/Target/AArch64/Disassembler/ |
| D | AArch64Disassembler.cpp | 1323 case AArch64::STLLRB: in DecodeExclusiveLdStInstruction()
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| /external/llvm-project/llvm/lib/Target/AArch64/ |
| D | AArch64SchedThunderX3T110.td | 1988 (instrs STLLRB, STLLRH, STLLRW, STLLRX)>;
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| D | AArch64SchedThunderX2T99.td | 1857 (instrs STLLRB, STLLRH, STLLRW, STLLRX)>;
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| D | AArch64InstrInfo.td | 3500 def STLLRB : StoreRelease <0b00, 1, 0, 0, 0, GPR32, "stllrb">;
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/ |
| D | AArch64SchedThunderX2T99.td | 1857 (instrs STLLRB, STLLRH, STLLRW, STLLRX)>;
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| D | AArch64InstrInfo.td | 3294 def STLLRB : StoreRelease <0b00, 1, 0, 0, 0, GPR32, "stllrb">;
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| /external/vixl/doc/aarch64/ |
| D | supported-instructions-aarch64.md | 2519 ### STLLRB ### subsection
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| /external/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/AArch64/ |
| D | AArch64GenMCCodeEmitter.inc | 4294 UINT64_C(144669696), // STLLRB
12003 case AArch64::STLLRB:
20223 CEFBS_HasLOR, // STLLRB = 4281
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| D | AArch64GenAsmWriter.inc | 5243 2255013612U, // STLLRB
10633 28U, // STLLRB
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| D | AArch64GenAsmWriter1.inc | 6240 415436054U, // STLLRB
11630 56U, // STLLRB
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| D | AArch64GenInstrInfo.inc | 4296 STLLRB = 4281,
11180 …deledSideEffects), 0x1ULL, nullptr, nullptr, OperandInfo292, -1 ,nullptr }, // Inst #4281 = STLLRB
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| D | AArch64GenAsmMatcher.inc | 18746 …{ 5484 /* stllrb */, AArch64::STLLRB, Convert__Reg1_0__GPR64sp01_2, AMFBS_HasLOR, { MCK_GPR32, MCK…
26119 …{ 5484 /* stllrb */, AArch64::STLLRB, Convert__Reg1_0__GPR64sp01_2, AMFBS_HasLOR, { MCK_GPR32, MCK…
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| D | AArch64GenDisassemblerTables.inc | 8812 /* 41327 */ MCD::OPC_Decode, 185, 33, 168, 1, // Opcode: STLLRB
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64InstrInfo.td | 2485 def STLLRB : StoreRelease <0b00, 1, 0, 0, 0, GPR32, "stllrb">;
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