| /external/llvm/lib/Target/AMDGPU/ |
| D | AMDGPUAsmPrinter.cpp | 117 const AMDGPUSubtarget &STM = MF->getSubtarget<AMDGPUSubtarget>(); in EmitFunctionBodyStart() local
119 if (STM.isAmdHsaOS()) { in EmitFunctionBodyStart()
127 const AMDGPUSubtarget &STM = MF->getSubtarget<AMDGPUSubtarget>(); in EmitFunctionEntryLabel() local
128 if (MFI->isKernel() && STM.isAmdHsaOS()) { in EmitFunctionEntryLabel()
159 const AMDGPUSubtarget &STM = MF.getSubtarget<AMDGPUSubtarget>(); in runOnMachineFunction() local
161 if (STM.getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS) { in runOnMachineFunction()
163 if (!STM.isAmdHsaOS()) { in runOnMachineFunction()
181 if (STM.getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS) { in runOnMachineFunction()
233 if (STM.dumpCode()) { in runOnMachineFunction()
253 const R600Subtarget &STM = MF.getSubtarget<R600Subtarget>(); in EmitProgramInfoR600() local
[all …]
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| D | SILoadStoreOptimizer.cpp | 414 const SISubtarget &STM = MF.getSubtarget<SISubtarget>(); in runOnMachineFunction() local
415 if (!STM.loadStoreOptEnabled()) in runOnMachineFunction()
418 TII = STM.getInstrInfo(); in runOnMachineFunction()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
| D | AMDGPUAsmPrinter.cpp | 196 const GCNSubtarget &STM = MF->getSubtarget<GCNSubtarget>(); in EmitFunctionBodyStart() local
198 if (!STM.hasCodeObjectV3() && STM.isAmdHsaOrMesa(F) && in EmitFunctionBodyStart()
206 if (STM.isAmdHsaOS()) in EmitFunctionBodyStart()
258 const GCNSubtarget &STM = MF->getSubtarget<GCNSubtarget>(); in EmitFunctionEntryLabel() local
259 if (MFI->isEntryFunction() && STM.isAmdHsaOrMesa(MF->getFunction())) { in EmitFunctionEntryLabel()
430 const GCNSubtarget &STM = MF.getSubtarget<GCNSubtarget>(); in runOnMachineFunction() local
433 if (!STM.isAmdHsaOS() && !STM.isAmdPalOS()) { in runOnMachineFunction()
449 if (STM.isAmdPalOS()) in runOnMachineFunction()
451 else if (!STM.isAmdHsaOS()) { in runOnMachineFunction()
456 if (STM.dumpCode()) { in runOnMachineFunction()
[all …]
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| D | R600AsmPrinter.cpp | 47 const R600Subtarget &STM = MF.getSubtarget<R600Subtarget>(); in EmitProgramInfoR600() local
48 const R600RegisterInfo *RI = STM.getRegisterInfo(); in EmitProgramInfoR600()
71 if (STM.getGeneration() >= AMDGPUSubtarget::EVERGREEN) { in EmitProgramInfoR600()
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| D | SILoadStoreOptimizer.cpp | 182 const GCNSubtarget &STM);
201 const GCNSubtarget *STM = nullptr; member in __anona8c9c02a0111::SILoadStoreOptimizer
214 static bool widthsFit(const GCNSubtarget &STM, const CombineInfo &CI,
469 const GCNSubtarget &STM) { in setMI() argument
489 EltSize = AMDGPU::getSMRDEncodedOffset(STM, 4); in setMI()
809 bool SILoadStoreOptimizer::widthsFit(const GCNSubtarget &STM, in widthsFit() argument
815 return (Width <= 4) && (STM.hasDwordx3LoadStores() || (Width != 3)); in widthsFit()
910 Paired.setMI(MBBI, *TII, *STM); in findMatchingInst()
917 : widthsFit(*STM, CI, Paired) && offsetsCanBeCombined(CI, *STI, Paired); in findMatchingInst()
939 if (STM->ldsRequiresM0Init()) in read2Opcode()
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| D | AMDGPUHSAMetadataStreamer.cpp | 213 const GCNSubtarget &STM = MF.getSubtarget<GCNSubtarget>(); in getHSACodeProps() local
222 HSACodeProps.mKernargSegmentSize = STM.getKernArgSegmentSize(F, in getHSACodeProps()
228 HSACodeProps.mWavefrontSize = STM.getWavefrontSize(); in getHSACodeProps()
233 HSACodeProps.mIsXNACKEnabled = STM.isXNACKEnabled(); in getHSACodeProps()
891 const GCNSubtarget &STM = MF.getSubtarget<GCNSubtarget>(); in getHSAKernelProps() local
899 STM.getKernArgSegmentSize(F, MaxKernArgAlign)); in getHSAKernelProps()
907 Kern.getDocument()->getNode(STM.getWavefrontSize()); in getHSAKernelProps()
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| /external/llvm-project/llvm/lib/Target/AMDGPU/ |
| D | AMDGPUAsmPrinter.cpp | 208 const GCNSubtarget &STM = MF->getSubtarget<GCNSubtarget>(); in emitFunctionBodyStart() local
210 if ((STM.isMesaKernel(F) || isHsaAbiVersion2(getGlobalSTI())) && in emitFunctionBodyStart()
218 if (STM.isAmdHsaOS()) in emitFunctionBodyStart()
270 const GCNSubtarget &STM = MF->getSubtarget<GCNSubtarget>(); in emitFunctionEntryLabel() local
271 if (MFI->isEntryFunction() && STM.isAmdHsaOrMesa(MF->getFunction())) { in emitFunctionEntryLabel()
440 const GCNSubtarget &STM = MF.getSubtarget<GCNSubtarget>(); in runOnMachineFunction() local
443 if (!STM.isAmdHsaOS() && !STM.isAmdPalOS()) { in runOnMachineFunction()
459 if (STM.isAmdPalOS()) { in runOnMachineFunction()
464 } else if (!STM.isAmdHsaOS()) { in runOnMachineFunction()
469 if (STM.dumpCode()) { in runOnMachineFunction()
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| D | R600AsmPrinter.cpp | 47 const R600Subtarget &STM = MF.getSubtarget<R600Subtarget>(); in EmitProgramInfoR600() local
48 const R600RegisterInfo *RI = STM.getRegisterInfo(); in EmitProgramInfoR600()
71 if (STM.getGeneration() >= AMDGPUSubtarget::EVERGREEN) { in EmitProgramInfoR600()
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| D | SILoadStoreOptimizer.cpp | 186 const GCNSubtarget &STM);
205 const GCNSubtarget *STM = nullptr; member in __anonbd440fb60111::SILoadStoreOptimizer
502 const GCNSubtarget &STM) { in setMI() argument
522 EltSize = AMDGPU::convertSMRDOffsetUnits(STM, 4); in setMI()
848 bool SILoadStoreOptimizer::widthsFit(const GCNSubtarget &STM, in widthsFit() argument
854 return (Width <= 4) && (STM.hasDwordx3LoadStores() || (Width != 3)); in widthsFit()
877 (!widthsFit(*STM, CI, Paired) || !offsetsCanBeCombined(CI, *STM, Paired))) in checkAndPrepareMerge()
976 offsetsCanBeCombined(CI, *STM, Paired, true); in checkAndPrepareMerge()
995 if (STM->ldsRequiresM0Init()) in read2Opcode()
1001 if (STM->ldsRequiresM0Init()) in read2ST64Opcode()
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| D | AMDGPUHSAMetadataStreamer.cpp | 198 const GCNSubtarget &STM = MF.getSubtarget<GCNSubtarget>(); in getHSACodeProps() local
207 HSACodeProps.mKernargSegmentSize = STM.getKernArgSegmentSize(F, in getHSACodeProps()
213 HSACodeProps.mWavefrontSize = STM.getWavefrontSize(); in getHSACodeProps()
218 HSACodeProps.mIsXNACKEnabled = STM.isXNACKEnabled(); in getHSACodeProps()
856 const GCNSubtarget &STM = MF.getSubtarget<GCNSubtarget>(); in getHSAKernelProps() local
864 STM.getKernArgSegmentSize(F, MaxKernArgAlign)); in getHSAKernelProps()
872 Kern.getDocument()->getNode(STM.getWavefrontSize()); in getHSAKernelProps()
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| /external/llvm-project/llvm/test/CodeGen/Thumb/ |
| D | stm-scavenging.ll | 4 ; Use STM to save the three registers
22 ; Don't use STM: there is no available register to store
|
| /external/OpenCSD/decoder/tests/snapshots/stm-issue-27/ |
| D | device_0.ini | 4 type=STM
|
| /external/OpenCSD/decoder/tests/snapshots/stm_only/ |
| D | device_0.ini | 4 type=STM
|
| /external/OpenCSD/decoder/tests/snapshots/juno_r1_1/ |
| D | device_12.ini | 4 type=STM
|
| /external/OpenCSD/decoder/tests/snapshots-ete/infrastructure/ |
| D | device_12.ini | 4 type=STM
|
| /external/OpenCSD/decoder/tests/snapshots/stm_only-2/ |
| D | device_0.ini | 4 type=STM
|
| /external/OpenCSD/decoder/tests/snapshots/stm_only-juno/ |
| D | device_0.ini | 4 type=STM
|
| /external/rust/crates/ring/tests/ |
| D | rsa_pss_sign_tests.txt | 2 # http://csrc.nist.gov/groups/STM/cavp/documents/dss/186-3rsatestvectors.zip
4 # http://csrc.nist.gov/groups/STM/cavp/digital-signatures.html#test-vectors
|
| /external/arm-trusted-firmware/docs/plat/marvell/armada/misc/ |
| D | mvebu-a8k-addr-map.rst | 25 …| - | | +--------- AP STM |…
|
| /external/llvm-project/llvm/test/CodeGen/ARM/ |
| D | cortex-a57-misched-stm.ll | 6 ; We need second, post-ra scheduling to have STM instruction combined from single-stores
|
| D | cortex-a57-misched-stm-wrback.ll | 6 ; We need second, post-ra scheduling to have STM instruction combined from single-stores
|
| /external/python/cryptography/vectors/cryptography_vectors/hashes/SHA1/ |
| D | Readme.txt | 17 http://csrc.nist.gov/groups/STM/cavp/documents/shs/SHAVS.pdf.
|
| /external/python/cryptography/vectors/cryptography_vectors/hashes/SHA2/ |
| D | Readme.txt | 17 http://csrc.nist.gov/groups/STM/cavp/documents/shs/SHAVS.pdf.
|
| /external/rust/crates/ring/src/ec/suite_b/ecdsa/ |
| D | ecdsa_sign_asn1_tests.txt | 2 # http://csrc.nist.gov/groups/STM/cavp/documents/dss/186-3ecdsatestvectors.zip
|
| /external/OpenCSD/ |
| D | TODO | 9 systems with STM, unless a companion M class was present.
|