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/external/libxaac/decoder/armv8/
Dixheaacd_fft32x32_ld2_armv8.s49 SUB w7, w2, w4 //xl0_0 = x_0 - x_4
51 SUB w9, w3, w5 //xl0_1 = x_2 - x_6
62 SUB w11, w2, w4 //xl1_0 = x_1 - x_5
64 SUB w14, w3, w5 //xl1_1 = x_3 - x_7
68 SUB w4, w6, w8 //n20 = xh0_0 - xh0_1
69 SUB w5, w7, w14 //n30 = xl0_0 - xl1_1
76 SUB w3, w11, w9 //n11 = xl1_0 - xl0_1
77 SUB w4, w10, w12 //n21 = xh1_0 - xh1_1
94 SUB w7, w2, w4 //xl0_0 = x_0 - x_4
96 SUB w9, w3, w5 //xl0_1 = x_2 - x_6
[all …]
Dixheaacd_postradixcompute4.s52 SUB w5, w5, w9 // xl0_0 = x_0 - x_4
55 SUB w6, w6, w10 // xl1_0 = x_1 - x_5
58 SUB w7, w7, w11 // xl0_1 = x_2 - x_6
61 SUB w8, w8, w12 // xl1_1 = x_3 - x_7
64 SUB w14, w14, w10 // n20 = xh0_0 - xh0_1
67 SUB w9, w9, w11 // n21 = xh1_0 - xh1_1
70 SUB w5, w5, w8 // n30 = xl0_0 - xl1_1
73 SUB w6, w6, w7 // n11 = xl1_0 - xl0_1
96 SUB x0, x0, #92 // #4*3 + #14<<1 * 3 - 8
100 SUB w5, w5, w9
[all …]
Dixheaacd_sbr_imdct_using_fft.s109 SUB X5, X5, X1, LSL #1
113 SUB X5, X5, X1, LSL #2
120 SUB X6, X6, X1, LSL #1
124 SUB X6, X6, X1, LSL #2
132 SUB X7, X7, X1, LSL #1
139 SUB X11, X11, X1, LSL #1
147 SUB V9.4S, V0.4S, V4.4S
149 SUB X7, X7, X1, LSL #2
156 SUB V4.4S, V1.4S, V5.4S
158 SUB X11, X11, X1, LSL #2
[all …]
Dixheaacd_imdct_using_fft.s139 SUB X5, X5, X1, LSL #1
143 SUB X5, X5, X1, LSL #2
150 SUB X6, X6, X1, LSL #1
154 SUB X6, X6, X1, LSL #2
162 SUB X7, X7, X1, LSL #1
169 SUB X11, X11, X1, LSL #1
177 SUB v9.4S, v0.4S, v4.4S
179 SUB X7, X7, X1, LSL #2
186 SUB v4.4S, v1.4S, v5.4S
188 SUB X11, X11, X1, LSL #2
[all …]
/external/libxaac/decoder/armv7/
Dixheaacd_post_radix_compute4.s52 SUB r5, r5, r9
55 SUB r6, r6, r10
58 SUB r7, r7, r11
61 SUB r8, r8, r12
64 SUB r14, r14, r10
67 SUB r9, r9, r11
70 SUB r5, r5, r8
73 SUB r6, r6, r7
89 SUB r0, r0, #92
93 SUB r5, r5, r9
[all …]
Dixheaacd_fft32x32_ld2_armv7.s18 SUB r7, r2, r4 @xl0_0 = x_0 - x_4
20 SUB r9, r3, r5 @xl0_1 = x_2 - x_6
27 SUB r11, r2, r4 @xl1_0 = x_1 - x_5
29 SUB r14, r3, r5 @xl1_1 = x_3 - x_7
33 SUB r4, r6, r8 @n20 = xh0_0 - xh0_1
34 SUB r5, r7, r14 @n30 = xl0_0 - xl1_1
41 SUB r3, r11, r9 @n11 = xl1_0 - xl0_1
42 SUB r4, r10, r12 @n21 = xh1_0 - xh1_1
55 SUB r7, r2, r4 @xl0_0 = x_0 - x_4
57 SUB r9, r3, r5 @xl0_1 = x_2 - x_6
[all …]
Dixheaacd_fft_15_ld.s29 SUB r4, r4, r10 @ r4 = buf1a[2] - buf1a[8]@
33 SUB r8, r6, r8 @ r2 = buf1a[4] - buf1a[6]
35 SUB r6, r1, r12 @ (r1 - r3)
45 SUB r12, r1, r6, LSL #1 @ r3 = r1 - t@
63 SUB r8, r5, r11 @ s4 = buf1a[3] - buf1a[9]
67 SUB r7, r7, r9 @ s2 = buf1a[5] + buf1a[7]@
70 SUB r9, r6, r5 @ (s1 - s3)
80 SUB r5, r6, r9, LSL #1 @ s3 = s1 - t@
82 SUB r0, r0, #896 @ r0 -inp[160]
100 SUB r9, r6, r2 @ buf2[3] = s1 - r2
[all …]
Dixheaacd_mps_complex_fft_64_asm.s10 SUB sp, sp, #0x44
14 SUB r12, r0, #16 @dig_rev_shift = norm32(npoints) + 1 -16@
15 SUB r0, r0, #1
42 SUB r6, r4, r6, lsl#1 @x2r = x0r - (x2r << 1)@
43 SUB r7, r5, r7, lsl#1 @x2i = x0i - (x2i << 1)@
46 SUB r1, r8, r10, lsl#1 @x3r = x1r - (x3r << 1)@
47 SUB r11, r9, r11, lsl#1 @x3i = x1i - (x3i << 1)@
51 SUB r8, r4, r8, lsl#1 @x1r = x0r - (x1r << 1)@
52 SUB r9, r5, r9, lsl#1 @x1i = x0i - (x1i << 1)
54 SUB r7, r7, r1 @x2i = x2i - x3r@
[all …]
Dixheaacd_complex_ifft_p2.s8 SUB sp, sp, #0x44
12 SUB r12, r0, #16 @dig_rev_shift = norm32(npoints) + 1 -16@
13 SUB r0, r0, #1
57 SUB r6, r4, r6, lsl#1 @x2r = x0r - (x2r << 1)@
58 SUB r7, r5, r7, lsl#1 @x2i = x0i - (x2i << 1)@
61 SUB r1, r8, r10, lsl#1 @x3r = x1r - (x3r << 1)@
62 SUB r11, r9, r11, lsl#1 @x3i = x1i - (x3i << 1)@
66 SUB r8, r4, r8, lsl#1 @x1r = x0r - (x1r << 1)@
67 SUB r9, r5, r9, lsl#1 @x1i = x0i - (x1i << 1)
68 SUB r6, r6, r11 @x2r = x2r - x3i@
[all …]
Dixheaacd_complex_fft_p2.s8 SUB sp, sp, #0x44
12 SUB r12, r0, #16 @dig_rev_shift = norm32(npoints) + 1 -16@
13 SUB r0, r0, #1
57 SUB r6, r4, r6, lsl#1 @x2r = x0r - (x2r << 1)@
58 SUB r7, r5, r7, lsl#1 @x2i = x0i - (x2i << 1)@
61 SUB r1, r8, r10, lsl#1 @x3r = x1r - (x3r << 1)@
62 SUB r11, r9, r11, lsl#1 @x3i = x1i - (x3i << 1)@
66 SUB r8, r4, r8, lsl#1 @x1r = x0r - (x1r << 1)@
67 SUB r9, r5, r9, lsl#1 @x1i = x0i - (x1i << 1)
69 SUB r7, r7, r1 @x2i = x2i - x3r@
[all …]
Dixheaacd_radix4_bfly.s31 SUB sp, sp, #16
60 SUB r11, r6, r8
62 SUB r14, r7, r9
65 SUB r7, r10, r12
74 SUB r8, r8, r9
76 SUB r6, r6, r10
80 SUB r12, r12, r9
83 SUB r10, r11, r6
86 SUB r6, r8, r14
92 SUB r8, r8, r14
[all …]
/external/llvm-project/llvm/test/CodeGen/Hexagon/
Dverify-liveness-at-def.mir5 …rify-machineinstrs -run-pass simple-register-coalescing 2>&1 | FileCheck -check-prefix=CHECK-SUB %s
38 # CHECK-SUB-NOT: Bad machine code
40 # CHECK-SUB: Bad machine code: Live range continues after dead def flag
42 # CHECK-SUB: v. register: %0
43 # CHECK-SUB: lanemask: 0000000000000002
45 # CHECK-SUB-NOT: Bad machine code
47 # CHECK-SUB: Bad machine code: Live range continues after dead def flag
48 # CHECK-SUB-NEXT: function: test_fail
49 # CHECK-SUB: v. register: %1
50 # CHECK-SUB: lanemask: 0000000000000002
[all …]
/external/llvm-project/llvm/test/Transforms/InstCombine/
Dsub-or-and-xor.ll8 ; CHECK-NEXT: [[SUB:%.*]] = xor i32 [[X:%.*]], [[Y:%.*]]
9 ; CHECK-NEXT: ret i32 [[SUB]]
19 ; CHECK-NEXT: [[SUB:%.*]] = xor i32 [[X:%.*]], [[Y:%.*]]
20 ; CHECK-NEXT: call void @use(i32 [[SUB]])
21 ; CHECK-NEXT: ret i32 [[SUB]]
34 ; CHECK-NEXT: [[SUB:%.*]] = xor i32 [[X]], [[Y]]
35 ; CHECK-NEXT: ret i32 [[SUB]]
48 ; CHECK-NEXT: [[SUB:%.*]] = xor i32 [[X]], [[Y]]
49 ; CHECK-NEXT: ret i32 [[SUB]]
60 ; CHECK-NEXT: [[SUB:%.*]] = xor i32 [[X:%.*]], [[Y:%.*]]
[all …]
Dsub-and-or-neg-xor.ll9 ; CHECK-NEXT: [[SUB:%.*]] = sub i32 0, [[TMP1]]
10 ; CHECK-NEXT: ret i32 [[SUB]]
21 ; CHECK-NEXT: [[SUB:%.*]] = sub i32 0, [[TMP1]]
22 ; CHECK-NEXT: call void @use(i32 [[SUB]])
23 ; CHECK-NEXT: ret i32 [[SUB]]
37 ; CHECK-NEXT: [[SUB:%.*]] = sub i32 0, [[TMP1]]
38 ; CHECK-NEXT: ret i32 [[SUB]]
52 ; CHECK-NEXT: [[SUB:%.*]] = sub i32 0, [[TMP1]]
53 ; CHECK-NEXT: ret i32 [[SUB]]
65 ; CHECK-NEXT: [[SUB:%.*]] = sub i32 0, [[TMP1]]
[all …]
Dsub-xor-or-neg-and.ll9 ; CHECK-NEXT: [[SUB:%.*]] = sub i32 0, [[TMP1]]
10 ; CHECK-NEXT: ret i32 [[SUB]]
21 ; CHECK-NEXT: [[SUB:%.*]] = sub i32 0, [[TMP1]]
22 ; CHECK-NEXT: call void @use(i32 [[SUB]])
23 ; CHECK-NEXT: ret i32 [[SUB]]
37 ; CHECK-NEXT: [[SUB:%.*]] = sub i32 0, [[TMP1]]
38 ; CHECK-NEXT: ret i32 [[SUB]]
52 ; CHECK-NEXT: [[SUB:%.*]] = sub i32 0, [[TMP1]]
53 ; CHECK-NEXT: ret i32 [[SUB]]
65 ; CHECK-NEXT: [[SUB:%.*]] = sub i32 0, [[TMP1]]
[all …]
Dabs_abs.ll7 ; CHECK-NEXT: [[SUB:%.*]] = sub nsw i32 0, [[X]]
8 ; CHECK-NEXT: [[COND:%.*]] = select i1 [[CMP]], i32 [[SUB]], i32 [[X]]
23 ; CHECK-NEXT: [[SUB:%.*]] = sub nsw <2 x i32> zeroinitializer, [[X]]
24 ; CHECK-NEXT: [[COND:%.*]] = select <2 x i1> [[CMP]], <2 x i32> [[SUB]], <2 x i32> [[X]]
39 ; CHECK-NEXT: [[SUB:%.*]] = sub nsw i32 0, [[X]]
40 ; CHECK-NEXT: [[COND:%.*]] = select i1 [[CMP]], i32 [[SUB]], i32 [[X]]
55 ; CHECK-NEXT: [[SUB:%.*]] = sub nsw i32 0, [[X]]
56 ; CHECK-NEXT: [[COND:%.*]] = select i1 [[CMP]], i32 [[SUB]], i32 [[X]]
71 ; CHECK-NEXT: [[SUB:%.*]] = sub nsw i32 0, [[X]]
72 ; CHECK-NEXT: [[COND:%.*]] = select i1 [[CMP]], i32 [[SUB]], i32 [[X]]
[all …]
/external/libhevc/decoder/arm/
Dihevcd_fmt_conv_420sp_to_420p.s102 SUB r10,r7,r8 @// Src Y increment
103 SUB r11,r5,r8 @// Dst Y increment
117 SUB r6,r6,#16
129 SUB r0,r0,r6
130 SUB r2,r2,r6
150 SUB r10,r7,r8 @// Src UV increment
152 SUB r11,r5,r11 @// Dst U and V increment
168 SUB r6,r6,#16
183 SUB r1,r1,r6
184 SUB r3,r3,r6,LSR #1
[all …]
Dihevcd_fmt_conv_420sp_to_420sp.s98 SUB r10,r7,r8 @// Src Y increment
99 SUB r11,r5,r8 @// Dst Y increment
109 SUB r6,r6,#32
127 SUB r0,r0,r6
128 SUB R2,R2,r6
156 SUB r10,r7,r8 @// Src UV increment
157 SUB r11,r5,r8 @// Dst UV increment
166 SUB r6,r6,#16
180 SUB r1,r1,r6
181 SUB R2,R2,r6
/external/libhevc/common/arm64/
Dihevc_sao_edge_offset_class2.s87 SUB x9,x7,#1 //wd - 1
100 …SUB sp,sp,#0xA0 //Decrement the stack pointer to store some temp arr values
103 SUB x10,x8,#1 //ht-1
156 SUB x10,x7,#1 //wd - 1
157 SUB x11,x8,#1 //ht - 1
163 SUB x4,x12,x1 //pu1_src[(wd - 1 + (ht - 1) * src_strd) - src_strd]
164 SUB x4,x4,#1
211 SUB x20,x12,#1 //ht_tmp--
223 SUB x20,x12,#1 //ht_tmp--
258 SUB x20,x0,x1 //pu1_src - src_strd
[all …]
Dihevc_sao_edge_offset_class3.s94 SUB x9,x7,#1 //wd - 1
100 …SUB sp,sp,#0xA0 //Decrement the stack pointer to store some temp arr values
103 SUB x10,x8,#1 //ht-1
116 SUB x10,x7,#1 //[wd - 1]
121 SUB x10,x10,#1 //[wd - 1 - 1]
124 SUB x12,x9,x11 //pu1_src[wd - 1] - pu1_src_top_right[0]
132 SUB x11,x9,x14 //pu1_src[wd - 1] - pu1_src[wd - 1 - 1 + src_strd]
160 SUB x11,x8,#1 //ht - 1
169 SUB x11,x12,x1 //pu1_src[(ht - 1) * src_strd) - src_strd]
175 SUB x14,x10,x14 //pu1_src[(ht - 1) * src_strd] - pu1_src_bot_left[0]
[all …]
Dihevc_sao_edge_offset_class3_chroma.s100 SUB x9,x7,#2 //wd - 2
111 …SUB sp,sp,#0xE0 //Decrement the stack pointer to store some temp arr values
114 SUB x10,x8,#1 //ht-1
127 SUB x14,x7,#2 //[wd - 2]
129 SUB x11,x7,#1 //[wd - 1]
135 SUB x12,x9,x11 //pu1_src[wd - 2] - pu1_src_top_right[0]
142 SUB x14,x14,#2 //[wd - 2 - 2]
144 SUB x11,x9,x14 //pu1_src[wd - 2] - pu1_src[wd - 2 - 2 + src_strd]
171 SUB x12,x10,x11 //pu1_src[wd - 1] - pu1_src_top_right[1]
178 SUB x14,x7,#3 //[wd - 1 - 2]
[all …]
/external/clang/test/Index/
Dcomplete-ivar-access.m53 …ex-test -code-completion-at=%s:43:8 -fobjc-nonfragile-abi %s | FileCheck -check-prefix=CHECK-SUB %s
54 …ex-test -code-completion-at=%s:48:8 -fobjc-nonfragile-abi %s | FileCheck -check-prefix=CHECK-SUB %s
55 // CHECK-SUB: ObjCIvarDecl:{ResultType int}{TypedText sub_private} (35)
56 // CHECK-SUB: ObjCIvarDecl:{ResultType int}{TypedText sub_protected} (35)
57 // CHECK-SUB: ObjCIvarDecl:{ResultType int}{TypedText sub_public} (35)
58 // CHECK-SUB: ObjCIvarDecl:{ResultType int}{TypedText super_ext_private} (35) (inaccessible)
59 // CHECK-SUB: ObjCIvarDecl:{ResultType int}{TypedText super_ext_protected} (35)
60 // CHECK-SUB: ObjCIvarDecl:{ResultType int}{TypedText super_ext_public} (35)
61 // CHECK-SUB: ObjCIvarDecl:{ResultType int}{TypedText super_private} (37) (inaccessible)
62 // CHECK-SUB: ObjCIvarDecl:{ResultType int}{TypedText super_protected} (37)
[all …]
/external/llvm-project/clang/test/Index/
Dcomplete-ivar-access.m53 …ex-test -code-completion-at=%s:43:8 -fobjc-nonfragile-abi %s | FileCheck -check-prefix=CHECK-SUB %s
54 …ex-test -code-completion-at=%s:48:8 -fobjc-nonfragile-abi %s | FileCheck -check-prefix=CHECK-SUB %s
55 // CHECK-SUB: ObjCIvarDecl:{ResultType int}{TypedText sub_private} (35)
56 // CHECK-SUB: ObjCIvarDecl:{ResultType int}{TypedText sub_protected} (35)
57 // CHECK-SUB: ObjCIvarDecl:{ResultType int}{TypedText sub_public} (35)
58 // CHECK-SUB: ObjCIvarDecl:{ResultType int}{TypedText super_ext_private} (35) (inaccessible)
59 // CHECK-SUB: ObjCIvarDecl:{ResultType int}{TypedText super_ext_protected} (35)
60 // CHECK-SUB: ObjCIvarDecl:{ResultType int}{TypedText super_ext_public} (35)
61 // CHECK-SUB: ObjCIvarDecl:{ResultType int}{TypedText super_private} (37) (inaccessible)
62 // CHECK-SUB: ObjCIvarDecl:{ResultType int}{TypedText super_protected} (37)
[all …]
/external/libhevc/decoder/arm64/
Dihevcd_fmt_conv_420sp_to_420p.s99 SUB x10,x7,x8 //// Src Y increment
100 SUB x11,x5,x8 //// Dst Y increment
115 SUB x6,x6,#16
128 SUB x0,x0,x6
129 SUB x2,x2,x6
151 SUB x10,x7,x8 //// Src UV increment
153 SUB x11,x5,x11 //// Dst U and V increment
170 SUB x6,x6,#16
186 SUB x1,x1,x6
187 SUB x3,x3,x6,LSR #1
[all …]
Dihevcd_fmt_conv_420sp_to_420sp.s102 SUB x10,x7,x8 //// Src Y increment
103 SUB x11,x5,x8 //// Dst Y increment
113 SUB x6,x6,#32
132 SUB x0,x0,x6
133 SUB x2,x2,x6
161 SUB x10,x7,x8 //// Src UV increment
162 SUB x11,x5,x8 //// Dst UV increment
171 SUB x6,x6,#16
186 SUB x1,x1,x6
187 SUB x2,x2,x6

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