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Searched refs:SUB2 (Results 1 – 25 of 51) sorted by relevance

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/external/llvm/lib/Fuzzer/test/
Dfuzzer-dirs.test2 RUN: mkdir -p %t/SUB1/SUB2/SUB3
4 RUN: echo b > %t/SUB1/SUB2/b
5 RUN: echo c > %t/SUB1/SUB2/SUB3/c
/external/libaom/libaom/av1/encoder/mips/msa/
Dfdct4x4_msa.c25 SUB2(in4, in1, in4, in2, in1, in2); in av1_fwht4x4_msa()
34 SUB2(in4, in2, in4, in3, in2, in3); in av1_fwht4x4_msa()
/external/libvpx/libvpx/vpx_dsp/mips/
Dfwd_dct32x32_msa.c96 SUB2(vec4, vec5, vec7, vec6, vec4, vec7); in fdct8x32_1d_column_even_store()
112 SUB2(in0, in1, in2, in3, in0, in2); in fdct8x32_1d_column_even_store()
118 SUB2(in9, vec2, in14, vec5, vec2, vec5); in fdct8x32_1d_column_even_store()
193 SUB2(in27, in26, in25, in24, in22, in21); in fdct8x32_1d_column_odd_store()
201 SUB2(in26, in27, in24, in25, in23, in20); in fdct8x32_1d_column_odd_store()
227 SUB2(in28, in29, in31, in30, in17, in18); in fdct8x32_1d_column_odd_store()
234 SUB2(in29, in28, in30, in31, in16, in19); in fdct8x32_1d_column_odd_store()
354 SUB2(vec4, vec5, vec7, vec6, vec4, vec7); in fdct8x32_1d_row_even_4x()
371 SUB2(in0, in1, in2, in3, in0, in2); in fdct8x32_1d_row_even_4x()
377 SUB2(in9, vec2, in14, vec5, vec2, vec5); in fdct8x32_1d_row_even_4x()
[all …]
Didct32x32_msa.c160 SUB2(reg5, reg4, reg3, reg2, vec0, vec1); in idct32x8_row_odd_process_store()
218 SUB2(reg0, reg4, reg1, reg5, vec0, vec1); in idct32x8_row_odd_process_store()
221 SUB2(reg2, reg6, reg3, reg7, vec0, vec1); in idct32x8_row_odd_process_store()
232 SUB2(reg0, reg4, reg3, reg7, vec0, vec1); in idct32x8_row_odd_process_store()
235 SUB2(reg1, reg5, reg2, reg6, vec0, vec1); in idct32x8_row_odd_process_store()
465 SUB2(reg5, reg4, reg3, reg2, vec0, vec1); in idct8x32_column_odd_process_store()
517 SUB2(reg0, reg4, reg1, reg5, vec0, vec1); in idct8x32_column_odd_process_store()
520 SUB2(reg2, reg6, reg3, reg7, vec0, vec1); in idct8x32_column_odd_process_store()
531 SUB2(reg0, reg4, reg3, reg7, vec0, vec1); in idct8x32_column_odd_process_store()
534 SUB2(reg1, reg5, reg2, reg6, vec0, vec1); in idct8x32_column_odd_process_store()
/external/llvm-project/llvm/test/CodeGen/AMDGPU/GlobalISel/
Dlegalize-ssubsat.mir29 ; GFX6: [[SUB2:%[0-9]+]]:_(s32) = G_SUB [[SHL]], [[SMIN1]]
30 ; GFX6: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SUB2]], [[C]](s32)
50 ; GFX8: [[SUB2:%[0-9]+]]:_(s16) = G_SUB [[SHL]], [[SMIN1]]
51 ; GFX8: [[ASHR:%[0-9]+]]:_(s16) = G_ASHR [[SUB2]], [[C]](s16)
98 ; GFX6: [[SUB2:%[0-9]+]]:_(s32) = G_SUB [[SHL]], [[SMIN1]]
99 ; GFX6: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SUB2]], [[C]](s32)
119 ; GFX8: [[SUB2:%[0-9]+]]:_(s16) = G_SUB [[SHL]], [[SMIN1]]
120 ; GFX8: [[ASHR:%[0-9]+]]:_(s16) = G_ASHR [[SUB2]], [[C]](s16)
175 ; GFX6: [[SUB2:%[0-9]+]]:_(s32) = G_SUB [[SHL]], [[SMIN1]]
176 ; GFX6: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SUB2]], [[C2]](s32)
[all …]
Dlegalize-saddsat.mir182 ; GFX6: [[SUB2:%[0-9]+]]:_(s32) = G_SUB [[C3]], [[SMAX2]]
186 ; GFX6: [[SMIN3:%[0-9]+]]:_(s32) = G_SMIN [[SMAX3]], [[SUB2]]
234 ; GFX8: [[SUB2:%[0-9]+]]:_(s16) = G_SUB [[C4]], [[SMAX2]]
238 ; GFX8: [[SMIN3:%[0-9]+]]:_(s16) = G_SMIN [[SMAX3]], [[SUB2]]
395 ; GFX6: [[SUB2:%[0-9]+]]:_(s32) = G_SUB [[C1]], [[SMAX2]]
399 ; GFX6: [[SMIN3:%[0-9]+]]:_(s32) = G_SMIN [[SMAX3]], [[SUB2]]
434 ; GFX8: [[SUB2:%[0-9]+]]:_(s16) = G_SUB [[C1]], [[SMAX2]]
438 ; GFX8: [[SMIN3:%[0-9]+]]:_(s16) = G_SMIN [[SMAX3]], [[SUB2]]
496 ; GFX6: [[SUB2:%[0-9]+]]:_(s32) = G_SUB [[C1]], [[SMAX2]]
500 ; GFX6: [[SMIN3:%[0-9]+]]:_(s32) = G_SMIN [[SMAX3]], [[SUB2]]
[all …]
Dlegalize-sub.mir195 ; GFX6: [[SUB2:%[0-9]+]]:_(s32) = G_SUB [[COPY10]], [[COPY11]]
196 ; GFX6: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[SUB2]](s32)
213 ; GFX8: [[SUB2:%[0-9]+]]:_(s16) = G_SUB [[TRUNC2]], [[TRUNC5]]
214 ; GFX8: S_ENDPGM 0, implicit [[SUB]](s16), implicit [[SUB1]](s16), implicit [[SUB2]](s16)
293 ; GFX6: [[SUB2:%[0-9]+]]:_(s32) = G_SUB [[COPY6]], [[COPY7]]
305 ; GFX6: [[COPY12:%[0-9]+]]:_(s32) = COPY [[SUB2]](s32)
338 ; GFX8: [[SUB2:%[0-9]+]]:_(s16) = G_SUB [[TRUNC2]], [[TRUNC6]]
345 ; GFX8: [[ZEXT2:%[0-9]+]]:_(s32) = G_ZEXT [[SUB2]](s16)
Dlegalize-fptosi.mir400 ; SI: [[SUB2:%[0-9]+]]:_(s32) = G_SUB [[C1]], [[SUB]]
402 ; SI: [[LSHR1:%[0-9]+]]:_(s64) = G_LSHR [[ZEXT]], [[SUB2]](s32)
435 ; VI: [[SUB2:%[0-9]+]]:_(s32) = G_SUB [[C1]], [[SUB]]
437 ; VI: [[LSHR1:%[0-9]+]]:_(s64) = G_LSHR [[ZEXT]], [[SUB2]](s32)
482 ; SI: [[SUB2:%[0-9]+]]:_(s32) = G_SUB [[C1]], [[SUB]]
484 ; SI: [[LSHR1:%[0-9]+]]:_(s64) = G_LSHR [[ZEXT]], [[SUB2]](s32)
542 ; VI: [[SUB2:%[0-9]+]]:_(s32) = G_SUB [[C1]], [[SUB]]
544 ; VI: [[LSHR1:%[0-9]+]]:_(s64) = G_LSHR [[ZEXT]], [[SUB2]](s32)
Dlegalize-ssubo.mir235 ; CHECK: [[SUB2:%[0-9]+]]:_(s32) = G_SUB [[COPY6]], [[COPY7]]
254 ; CHECK: [[COPY12:%[0-9]+]]:_(s32) = COPY [[SUB2]](s32)
297 ; CHECK: [[COPY19:%[0-9]+]]:_(s32) = COPY [[SUB2]](s32)
362 ; CHECK: [[SUB2:%[0-9]+]]:_(s32) = G_SUB [[COPY6]], [[COPY7]]
374 ; CHECK: [[COPY12:%[0-9]+]]:_(s32) = COPY [[SUB2]](s32)
398 ; CHECK: [[COPY18:%[0-9]+]]:_(s32) = COPY [[SUB2]](s32)
Dlegalize-udiv.mir32 ; GFX6: [[SUB2:%[0-9]+]]:_(s32) = G_SUB [[SUB1]], [[COPY1]]
33 ; GFX6: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s1), [[SUB2]], [[SUB1]]
58 ; GFX8: [[SUB2:%[0-9]+]]:_(s32) = G_SUB [[SUB1]], [[COPY1]]
59 ; GFX8: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s1), [[SUB2]], [[SUB1]]
84 ; GFX9: [[SUB2:%[0-9]+]]:_(s32) = G_SUB [[SUB1]], [[COPY1]]
85 ; GFX9: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s1), [[SUB2]], [[SUB1]]
124 ; GFX6: [[SUB2:%[0-9]+]]:_(s32) = G_SUB [[SUB1]], [[UV2]]
125 ; GFX6: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s1), [[SUB2]], [[SUB1]]
173 ; GFX8: [[SUB2:%[0-9]+]]:_(s32) = G_SUB [[SUB1]], [[UV2]]
174 ; GFX8: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s1), [[SUB2]], [[SUB1]]
[all …]
Dlegalize-urem.mir29 ; GFX6: [[SUB2:%[0-9]+]]:_(s32) = G_SUB [[SUB1]], [[COPY1]]
30 ; GFX6: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s1), [[SUB2]], [[SUB1]]
52 ; GFX8: [[SUB2:%[0-9]+]]:_(s32) = G_SUB [[SUB1]], [[COPY1]]
53 ; GFX8: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s1), [[SUB2]], [[SUB1]]
75 ; GFX9: [[SUB2:%[0-9]+]]:_(s32) = G_SUB [[SUB1]], [[COPY1]]
76 ; GFX9: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s1), [[SUB2]], [[SUB1]]
112 ; GFX6: [[SUB2:%[0-9]+]]:_(s32) = G_SUB [[SUB1]], [[UV2]]
113 ; GFX6: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s1), [[SUB2]], [[SUB1]]
156 ; GFX8: [[SUB2:%[0-9]+]]:_(s32) = G_SUB [[SUB1]], [[UV2]]
157 ; GFX8: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s1), [[SUB2]], [[SUB1]]
[all …]
Dlegalize-usube.mir51 ; CHECK: [[SUB2:%[0-9]+]]:_(s32) = G_SUB [[SUB]], [[ZEXT]]
53 ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[SUB2]](s32), [[SUB3]](s32)
Dlegalize-sdiv.mir39 ; GFX6: [[SUB2:%[0-9]+]]:_(s32) = G_SUB [[SUB1]], [[XOR1]]
40 ; GFX6: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s1), [[SUB2]], [[SUB1]]
75 ; GFX8: [[SUB2:%[0-9]+]]:_(s32) = G_SUB [[SUB1]], [[XOR1]]
76 ; GFX8: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s1), [[SUB2]], [[SUB1]]
111 ; GFX9: [[SUB2:%[0-9]+]]:_(s32) = G_SUB [[SUB1]], [[XOR1]]
112 ; GFX9: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s1), [[SUB2]], [[SUB1]]
161 ; GFX6: [[SUB2:%[0-9]+]]:_(s32) = G_SUB [[SUB1]], [[XOR1]]
162 ; GFX6: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s1), [[SUB2]], [[SUB1]]
229 ; GFX8: [[SUB2:%[0-9]+]]:_(s32) = G_SUB [[SUB1]], [[XOR1]]
230 ; GFX8: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s1), [[SUB2]], [[SUB1]]
[all …]
Dlegalize-srem.mir36 ; GFX6: [[SUB2:%[0-9]+]]:_(s32) = G_SUB [[SUB1]], [[XOR1]]
37 ; GFX6: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s1), [[SUB2]], [[SUB1]]
68 ; GFX8: [[SUB2:%[0-9]+]]:_(s32) = G_SUB [[SUB1]], [[XOR1]]
69 ; GFX8: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s1), [[SUB2]], [[SUB1]]
100 ; GFX9: [[SUB2:%[0-9]+]]:_(s32) = G_SUB [[SUB1]], [[XOR1]]
101 ; GFX9: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s1), [[SUB2]], [[SUB1]]
146 ; GFX6: [[SUB2:%[0-9]+]]:_(s32) = G_SUB [[SUB1]], [[XOR1]]
147 ; GFX6: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s1), [[SUB2]], [[SUB1]]
207 ; GFX8: [[SUB2:%[0-9]+]]:_(s32) = G_SUB [[SUB1]], [[XOR1]]
208 ; GFX8: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s1), [[SUB2]], [[SUB1]]
[all …]
Dlegalize-usubo.mir199 ; CHECK: [[SUB2:%[0-9]+]]:_(s16) = G_SUB [[TRUNC2]], [[TRUNC5]]
236 ; CHECK: [[ZEXT2:%[0-9]+]]:_(s32) = G_ZEXT [[SUB2]](s16)
303 ; CHECK: [[SUB2:%[0-9]+]]:_(s16) = G_SUB [[TRUNC2]], [[TRUNC6]]
310 ; CHECK: [[ZEXT2:%[0-9]+]]:_(s32) = G_ZEXT [[SUB2]](s16)
Dlegalize-fptoui.mir400 ; SI: [[SUB2:%[0-9]+]]:_(s32) = G_SUB [[C1]], [[SUB]]
402 ; SI: [[LSHR1:%[0-9]+]]:_(s64) = G_LSHR [[ZEXT]], [[SUB2]](s32)
464 ; VI: [[SUB2:%[0-9]+]]:_(s32) = G_SUB [[C1]], [[SUB]]
466 ; VI: [[LSHR1:%[0-9]+]]:_(s64) = G_LSHR [[ZEXT]], [[SUB2]](s32)
540 ; SI: [[SUB2:%[0-9]+]]:_(s32) = G_SUB [[C1]], [[SUB]]
542 ; SI: [[LSHR1:%[0-9]+]]:_(s64) = G_LSHR [[ZEXT]], [[SUB2]](s32)
656 ; VI: [[SUB2:%[0-9]+]]:_(s32) = G_SUB [[C1]], [[SUB]]
658 ; VI: [[LSHR1:%[0-9]+]]:_(s64) = G_LSHR [[ZEXT]], [[SUB2]](s32)
/external/libvpx/libvpx/vp8/encoder/mips/msa/
Dquantize_msa.c58 SUB2(x0, sign_z0, x1, sign_z1, x0, x1); in fast_quantize_b_msa()
121 SUB2(x0, z_bin0, x1, z_bin1, z_bin0, z_bin1); in exact_regular_quantize_b_msa()
122 SUB2(z_bin0, zbin_o_q, z_bin1, zbin_o_q, z_bin0, z_bin1); in exact_regular_quantize_b_msa()
145 SUB2(sign_x0, sign_z0, sign_x1, sign_z1, sign_x0, sign_x1); in exact_regular_quantize_b_msa()
/external/libvpx/libvpx/vp9/encoder/mips/msa/
Dvp9_fdct4x4_msa.c26 SUB2(in4, in1, in4, in2, in1, in2); in vp9_fwht4x4_msa()
35 SUB2(in4, in2, in4, in3, in2, in3); in vp9_fwht4x4_msa()
/external/llvm-project/compiler-rt/test/fuzzer/
Dfuzzer-dirs.test4 RUN: mkdir -p %t/SUB1/SUB2/SUB3
6 RUN: echo b > %t/SUB1/SUB2/b
7 RUN: echo c > %t/SUB1/SUB2/SUB3/c
/external/webp/src/dsp/
Dlossless_enc_msa.c33 SUB2(t0, t2, t1, t3, t0, t1); \
109 SUB2(src0, tmp0, src1, tmp1, dst0, dst1); in SubtractGreenFromBlueAndRed_MSA()
Dfilters_msa.c31 SUB2(src0, pred0, src1, pred1, dst0, dst1); in PredictLineInverse0()
115 SUB2(a0, c0, a1, c1, a0, a1); in PredictLineGradient()
/external/llvm-project/llvm/test/Transforms/IndVarSimplify/
Dpredicated_ranges.ll122 ; CHECK-NEXT: [[SUB2:%.*]] = sub nsw i32 [[ARG]], [[I]]
123 ; CHECK-NEXT: [[SUB3:%.*]] = sub nsw i32 [[SUB2]], 1
181 ; CHECK-NEXT: [[SUB2:%.*]] = sub nsw i32 [[ARG]], [[I]]
182 ; CHECK-NEXT: [[SUB3:%.*]] = sub nsw i32 [[SUB2]], 1
239 ; CHECK-NEXT: [[SUB2:%.*]] = sub nsw i32 [[ARG]], [[I]]
240 ; CHECK-NEXT: [[SUB3:%.*]] = sub nsw i32 [[SUB2]], 1
298 ; CHECK-NEXT: [[SUB2:%.*]] = sub nsw i32 [[ARG]], [[I]]
299 ; CHECK-NEXT: [[SUB3:%.*]] = sub nsw i32 [[SUB2]], 1
359 ; CHECK-NEXT: [[SUB2:%.*]] = sub nsw i32 [[ARG]], [[I]]
360 ; CHECK-NEXT: [[SUB3:%.*]] = sub nsw i32 [[SUB2]], 1
[all …]
/external/llvm-project/llvm/test/Transforms/SimplifyCFG/PowerPC/
Dprefer-fma.ll40 ; CHECK-NEXT: [[SUB2:%.*]] = fsub fast double [[NEG]], 3.000000e+00
41 ; CHECK-NEXT: store double [[SUB2]], double* [[Y]], align 8
/external/llvm-project/llvm/test/CodeGen/Mips/GlobalISel/legalizer/
Dsub.mir236 ; MIPS32: [[SUB2:%[0-9]+]]:_(s32) = G_SUB [[SUB1]], [[AND]]
237 ; MIPS32: $v0 = COPY [[SUB2]](s32)
286 ; MIPS32: [[SUB2:%[0-9]+]]:_(s32) = G_SUB [[SUB1]], [[AND]]
310 ; MIPS32: $v1 = COPY [[SUB2]](s32)
/external/llvm-project/llvm/test/Transforms/InstCombine/
Dreassociate-nuw.ll84 ; CHECK-NEXT: [[SUB2:%.*]] = sub nuw i32 [[SUB0]], [[SUB1]]
85 ; CHECK-NEXT: ret i32 [[SUB2]]

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