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Searched refs:SUB4 (Results 1 – 25 of 25) sorted by relevance

/external/libaom/libaom/av1/encoder/mips/msa/
Dtemporal_filter_msa.c67 SUB4(cnst16, mod0_w, cnst16, mod1_w, cnst16, mod2_w, cnst16, mod3_w, mod0_w, in temporal_filter_apply_8size_msa()
114 SUB4(cnst16, mod0_w, cnst16, mod1_w, cnst16, mod2_w, cnst16, mod3_w, mod0_w, in temporal_filter_apply_8size_msa()
191 SUB4(cnst16, mod0_w, cnst16, mod1_w, cnst16, mod2_w, cnst16, mod3_w, mod0_w, in temporal_filter_apply_16size_msa()
238 SUB4(cnst16, mod0_w, cnst16, mod1_w, cnst16, mod2_w, cnst16, mod3_w, mod0_w, in temporal_filter_apply_16size_msa()
/external/libvpx/libvpx/vpx_dsp/mips/
Dfwd_dct32x32_msa.c88 SUB4(vec0, vec7, vec1, vec6, vec2, vec5, vec3, vec4, vec7, vec6, vec5, vec4); in fdct8x32_1d_column_even_store()
120 SUB4(in8, vec3, in15, vec4, in3, in2, in0, in1, in3, in0, vec2, vec5); in fdct8x32_1d_column_even_store()
199 SUB4(in17, in18, in16, in19, in31, in28, in30, in29, in23, in26, in24, in20); in fdct8x32_1d_column_odd_store()
219 SUB4(in23, in20, in22, in21, in25, in26, in24, in27, in28, in17, in18, in31); in fdct8x32_1d_column_odd_store()
346 SUB4(vec3, vec4, vec2, vec5, vec1, vec6, vec0, vec7, vec4, vec5, vec6, vec7); in fdct8x32_1d_row_even_4x()
379 SUB4(in8, vec3, in15, vec4, in3, in2, in0, in1, in3, in0, vec2, vec5); in fdct8x32_1d_row_even_4x()
419 SUB4(vec3, vec4, vec2, vec5, vec1, vec6, vec0, vec7, vec4, vec5, vec6, vec7); in fdct8x32_1d_row_even()
451 SUB4(in8, vec3, in15, vec4, in3, in2, in0, in1, in3, in0, vec2, vec5) in fdct8x32_1d_row_even()
535 SUB4(in17, in18, in16, in19, in31, in28, in30, in29, in23, in26, in24, in20); in fdct8x32_1d_row_odd()
565 SUB4(in23, in20, in22, in21, in25, in26, in24, in27, in28, in17, in18, in31); in fdct8x32_1d_row_odd()
[all …]
Didct32x32_msa.c190 SUB4(reg1, reg2, reg6, reg5, reg0, reg3, reg7, reg4, vec0, vec1, vec2, vec3); in idct32x8_row_odd_process_store()
494 SUB4(reg1, reg2, reg6, reg5, reg0, reg3, reg7, reg4, vec0, vec1, vec2, vec3); in idct8x32_column_odd_process_store()
559 SUB4(loc0, vec3, loc1, vec2, loc2, vec1, loc3, vec0, m6, m2, m4, m0); in idct8x32_column_butterfly_addblk()
578 SUB4(loc0, vec3, loc1, vec2, loc2, vec1, loc3, vec0, m7, m3, m5, m1); in idct8x32_column_butterfly_addblk()
597 SUB4(loc0, vec3, loc1, vec2, loc2, vec1, loc3, vec0, n6, n2, n4, n0); in idct8x32_column_butterfly_addblk()
616 SUB4(loc0, vec3, loc1, vec2, loc2, vec1, loc3, vec0, n7, n3, n5, n1); in idct8x32_column_butterfly_addblk()
Dinv_txfm_msa.h275 SUB4(r0_m, r4_m, r1_m, r5_m, r2_m, r6_m, r3_m, r7_m, m0_m, m1_m, m2_m, \
293 SUB4(r0_m, r4_m, r1_m, r5_m, r2_m, r6_m, r3_m, r7_m, m0_m, m1_m, m2_m, \
311 SUB4(r0_m, r6_m, r1_m, r7_m, r2_m, r4_m, r3_m, r5_m, m0_m, m1_m, m2_m, \
Dfwd_txfm_msa.c55 SUB4(in0, in15, in1, in14, in2, in13, in3, in12, in15, in14, in13, in12); in fdct8x16_1d_column()
56 SUB4(in4, in11, in5, in10, in6, in9, in7, in8, in11, in10, in9, in8); in fdct8x16_1d_column()
Didct16x16_msa.c35 SUB4(reg2, loc1, reg14, loc0, reg6, loc3, reg10, loc2, reg0, reg12, reg4, in vpx_idct16_1d_rows_msa()
Dmacros_msa.h1576 #define SUB4(in0, in1, in2, in3, in4, in5, in6, in7, out0, out1, out2, out3) \ macro
/external/libvpx/libvpx/vp8/encoder/mips/msa/
Dtemporal_filter_msa.c57 SUB4(const16, mod0_w, const16, mod1_w, const16, mod2_w, const16, mod3_w, in temporal_filter_apply_16size_msa()
95 SUB4(const16, mod0_w, const16, mod1_w, const16, mod2_w, const16, mod3_w, in temporal_filter_apply_16size_msa()
177 SUB4(const16, mod0_w, const16, mod1_w, const16, mod2_w, const16, mod3_w, in temporal_filter_apply_8size_msa()
217 SUB4(const16, mod0_w, const16, mod1_w, const16, mod2_w, const16, mod3_w, in temporal_filter_apply_8size_msa()
/external/llvm-project/llvm/test/CodeGen/AMDGPU/GlobalISel/
Dlegalize-ssubsat.mir184 ; GFX6: [[SUB4:%[0-9]+]]:_(s32) = G_SUB [[SMIN2]], [[C4]]
186 ; GFX6: [[SMIN3:%[0-9]+]]:_(s32) = G_SMIN [[SMAX3]], [[SUB4]]
236 ; GFX8: [[SUB4:%[0-9]+]]:_(s16) = G_SUB [[SMIN2]], [[C5]]
238 ; GFX8: [[SMIN3:%[0-9]+]]:_(s16) = G_SMIN [[SMAX3]], [[SUB4]]
397 ; GFX6: [[SUB4:%[0-9]+]]:_(s32) = G_SUB [[SMIN2]], [[C2]]
399 ; GFX6: [[SMIN3:%[0-9]+]]:_(s32) = G_SMIN [[SMAX3]], [[SUB4]]
436 ; GFX8: [[SUB4:%[0-9]+]]:_(s16) = G_SUB [[SMIN2]], [[C2]]
438 ; GFX8: [[SMIN3:%[0-9]+]]:_(s16) = G_SMIN [[SMAX3]], [[SUB4]]
498 ; GFX6: [[SUB4:%[0-9]+]]:_(s32) = G_SUB [[SMIN2]], [[C2]]
500 ; GFX6: [[SMIN3:%[0-9]+]]:_(s32) = G_SMIN [[SMAX3]], [[SUB4]]
[all …]
Dlegalize-srem.mir42 ; GFX6: [[SUB4:%[0-9]+]]:_(s32) = G_SUB [[XOR2]], [[ASHR]]
43 ; GFX6: $vgpr0 = COPY [[SUB4]](s32)
74 ; GFX8: [[SUB4:%[0-9]+]]:_(s32) = G_SUB [[XOR2]], [[ASHR]]
75 ; GFX8: $vgpr0 = COPY [[SUB4]](s32)
106 ; GFX9: [[SUB4:%[0-9]+]]:_(s32) = G_SUB [[XOR2]], [[ASHR]]
107 ; GFX9: $vgpr0 = COPY [[SUB4]](s32)
152 ; GFX6: [[SUB4:%[0-9]+]]:_(s32) = G_SUB [[XOR2]], [[ASHR]]
179 ; GFX6: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[SUB4]](s32), [[SUB9]](s32)
213 ; GFX8: [[SUB4:%[0-9]+]]:_(s32) = G_SUB [[XOR2]], [[ASHR]]
240 ; GFX8: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[SUB4]](s32), [[SUB9]](s32)
[all …]
Dlegalize-fptoui.mir426 ; SI: [[SUB4:%[0-9]+]]:_(s32) = G_SUB [[SUB3]], [[C1]]
428 ; SI: [[SHL1:%[0-9]+]]:_(s64) = G_SHL [[ZEXT1]], [[SUB4]](s32)
490 ; VI: [[SUB4:%[0-9]+]]:_(s32) = G_SUB [[SUB3]], [[C1]]
492 ; VI: [[SHL1:%[0-9]+]]:_(s64) = G_SHL [[ZEXT1]], [[SUB4]](s32)
566 ; SI: [[SUB4:%[0-9]+]]:_(s32) = G_SUB [[SUB3]], [[C1]]
568 ; SI: [[SHL1:%[0-9]+]]:_(s64) = G_SHL [[ZEXT1]], [[SUB4]](s32)
682 ; VI: [[SUB4:%[0-9]+]]:_(s32) = G_SUB [[SUB3]], [[C1]]
684 ; VI: [[SHL1:%[0-9]+]]:_(s64) = G_SHL [[ZEXT1]], [[SUB4]](s32)
Dlegalize-udiv.mir140 ; GFX6: [[SUB4:%[0-9]+]]:_(s32) = G_SUB [[UV1]], [[MUL3]]
141 ; GFX6: [[ICMP2:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[SUB4]](s32), [[UV3]]
144 ; GFX6: [[SUB5:%[0-9]+]]:_(s32) = G_SUB [[SUB4]], [[UV3]]
145 ; GFX6: [[SELECT4:%[0-9]+]]:_(s32) = G_SELECT [[ICMP2]](s1), [[SUB5]], [[SUB4]]
189 ; GFX8: [[SUB4:%[0-9]+]]:_(s32) = G_SUB [[UV1]], [[MUL3]]
190 ; GFX8: [[ICMP2:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[SUB4]](s32), [[UV3]]
193 ; GFX8: [[SUB5:%[0-9]+]]:_(s32) = G_SUB [[SUB4]], [[UV3]]
194 ; GFX8: [[SELECT4:%[0-9]+]]:_(s32) = G_SELECT [[ICMP2]](s1), [[SUB5]], [[SUB4]]
238 ; GFX9: [[SUB4:%[0-9]+]]:_(s32) = G_SUB [[UV1]], [[MUL3]]
239 ; GFX9: [[ICMP2:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[SUB4]](s32), [[UV3]]
[all …]
Dlegalize-fptosi.mir506 ; SI: [[SUB4:%[0-9]+]]:_(s32) = G_SUB [[SUB3]], [[C1]]
508 ; SI: [[SHL1:%[0-9]+]]:_(s64) = G_SHL [[ZEXT1]], [[SUB4]](s32)
566 ; VI: [[SUB4:%[0-9]+]]:_(s32) = G_SUB [[SUB3]], [[C1]]
568 ; VI: [[SHL1:%[0-9]+]]:_(s64) = G_SHL [[ZEXT1]], [[SUB4]](s32)
Dlegalize-saddsat.mir508 ; GFX6: [[SUB4:%[0-9]+]]:_(s32) = G_SUB [[C1]], [[SMAX4]]
512 ; GFX6: [[SMIN5:%[0-9]+]]:_(s32) = G_SMIN [[SMAX5]], [[SUB4]]
585 ; GFX8: [[SUB4:%[0-9]+]]:_(s16) = G_SUB [[C1]], [[SMAX4]]
589 ; GFX8: [[SMIN5:%[0-9]+]]:_(s16) = G_SMIN [[SMAX5]], [[SUB4]]
730 ; GFX6: [[SUB4:%[0-9]+]]:_(s32) = G_SUB [[C1]], [[SMAX4]]
734 ; GFX6: [[SMIN5:%[0-9]+]]:_(s32) = G_SMIN [[SMAX5]], [[SUB4]]
806 ; GFX8: [[SUB4:%[0-9]+]]:_(s16) = G_SUB [[C1]], [[SMAX4]]
810 ; GFX8: [[SMIN5:%[0-9]+]]:_(s16) = G_SMIN [[SMAX5]], [[SUB4]]
Dlegalize-urem.mir122 ; GFX6: [[SUB4:%[0-9]+]]:_(s32) = G_SUB [[C1]], [[UV3]]
123 ; GFX6: [[MUL2:%[0-9]+]]:_(s32) = G_MUL [[SUB4]], [[FPTOUI1]]
166 ; GFX8: [[SUB4:%[0-9]+]]:_(s32) = G_SUB [[C1]], [[UV3]]
167 ; GFX8: [[MUL2:%[0-9]+]]:_(s32) = G_MUL [[SUB4]], [[FPTOUI1]]
210 ; GFX9: [[SUB4:%[0-9]+]]:_(s32) = G_SUB [[C1]], [[UV3]]
211 ; GFX9: [[MUL2:%[0-9]+]]:_(s32) = G_MUL [[SUB4]], [[FPTOUI1]]
1712 ; GFX6: [[SUB4:%[0-9]+]]:_(s32) = G_SUB [[C3]], [[AND3]]
1713 ; GFX6: [[MUL2:%[0-9]+]]:_(s32) = G_MUL [[SUB4]], [[FPTOUI1]]
1774 ; GFX8: [[SUB4:%[0-9]+]]:_(s32) = G_SUB [[C3]], [[AND3]]
1775 ; GFX8: [[MUL2:%[0-9]+]]:_(s32) = G_MUL [[SUB4]], [[FPTOUI1]]
[all …]
Dlegalize-shl.mir1387 ; SI: [[SUB4:%[0-9]+]]:_(s32) = G_SUB [[SUB1]], [[C3]]
1395 ; SI: [[LSHR3:%[0-9]+]]:_(s64) = G_LSHR [[UV5]], [[SUB4]](s32)
1464 ; VI: [[SUB4:%[0-9]+]]:_(s32) = G_SUB [[SUB1]], [[C3]]
1472 ; VI: [[LSHR3:%[0-9]+]]:_(s64) = G_LSHR [[UV5]], [[SUB4]](s32)
1541 ; GFX9: [[SUB4:%[0-9]+]]:_(s32) = G_SUB [[SUB1]], [[C3]]
1549 ; GFX9: [[LSHR3:%[0-9]+]]:_(s64) = G_LSHR [[UV5]], [[SUB4]](s32)
Dlegalize-sdiv.mir180 ; GFX6: [[SUB4:%[0-9]+]]:_(s32) = G_SUB [[C2]], [[XOR5]]
181 ; GFX6: [[MUL2:%[0-9]+]]:_(s32) = G_MUL [[SUB4]], [[FPTOUI1]]
248 ; GFX8: [[SUB4:%[0-9]+]]:_(s32) = G_SUB [[C2]], [[XOR5]]
249 ; GFX8: [[MUL2:%[0-9]+]]:_(s32) = G_MUL [[SUB4]], [[FPTOUI1]]
316 ; GFX9: [[SUB4:%[0-9]+]]:_(s32) = G_SUB [[C2]], [[XOR5]]
317 ; GFX9: [[MUL2:%[0-9]+]]:_(s32) = G_MUL [[SUB4]], [[FPTOUI1]]
2129 ; GFX6: [[SUB4:%[0-9]+]]:_(s32) = G_SUB [[C3]], [[XOR5]]
2130 ; GFX6: [[MUL2:%[0-9]+]]:_(s32) = G_MUL [[SUB4]], [[FPTOUI1]]
2215 ; GFX8: [[SUB4:%[0-9]+]]:_(s32) = G_SUB [[C3]], [[XOR5]]
2216 ; GFX8: [[MUL2:%[0-9]+]]:_(s32) = G_MUL [[SUB4]], [[FPTOUI1]]
[all …]
Dlegalize-lshr.mir1465 ; SI: [[SUB4:%[0-9]+]]:_(s32) = G_SUB [[COPY1]], [[C3]]
1473 ; SI: [[LSHR5:%[0-9]+]]:_(s64) = G_LSHR [[UV5]], [[SUB4]](s32)
1542 ; VI: [[SUB4:%[0-9]+]]:_(s32) = G_SUB [[COPY1]], [[C3]]
1550 ; VI: [[LSHR5:%[0-9]+]]:_(s64) = G_LSHR [[UV5]], [[SUB4]](s32)
1619 ; GFX9: [[SUB4:%[0-9]+]]:_(s32) = G_SUB [[COPY1]], [[C3]]
1627 ; GFX9: [[LSHR5:%[0-9]+]]:_(s64) = G_LSHR [[UV5]], [[SUB4]](s32)
Dlegalize-ashr.mir1473 ; SI: [[SUB4:%[0-9]+]]:_(s32) = G_SUB [[COPY1]], [[C3]]
1481 ; SI: [[LSHR3:%[0-9]+]]:_(s64) = G_LSHR [[UV5]], [[SUB4]](s32)
1556 ; VI: [[SUB4:%[0-9]+]]:_(s32) = G_SUB [[COPY1]], [[C3]]
1564 ; VI: [[LSHR3:%[0-9]+]]:_(s64) = G_LSHR [[UV5]], [[SUB4]](s32)
1639 ; GFX9: [[SUB4:%[0-9]+]]:_(s32) = G_SUB [[COPY1]], [[C3]]
1647 ; GFX9: [[LSHR3:%[0-9]+]]:_(s64) = G_LSHR [[UV5]], [[SUB4]](s32)
/external/llvm-project/llvm/test/Transforms/SLPVectorizer/X86/
DPR31847.ll30 ; CHECK-NEXT: [[SUB4:%.*]] = add nsw i32 [[CONV3]], -128
34 ; CHECK-NEXT: [[CMP8:%.*]] = icmp sgt i32 [[SUB4]], -1
36 ; CHECK-NEXT: [[COND14:%.*]] = select i1 [[CMP8]], i32 [[SUB4]], i32 [[SUB12]]
/external/llvm-project/llvm/test/CodeGen/Mips/GlobalISel/legalizer/
Dsub.mir297 ; MIPS32: [[SUB4:%[0-9]+]]:_(s32) = G_SUB [[SUB3]], [[AND2]]
311 ; MIPS32: $a0 = COPY [[SUB4]](s32)
/external/webp/src/dsp/
Drescaler_msa.c281 SUB4(src0, frac0, src1, frac1, src2, frac2, src3, frac3,
Dmsa_macro.h1197 #define SUB4(in0, in1, in2, in3, in4, in5, in6, in7, \ macro
/external/libvpx/libvpx/vp8/common/mips/msa/
Dvp8_macros_msa.h1473 #define SUB4(in0, in1, in2, in3, in4, in5, in6, in7, out0, out1, out2, out3) \ macro
/external/libaom/libaom/aom_dsp/mips/
Dmacros_msa.h1680 #define SUB4(in0, in1, in2, in3, in4, in5, in6, in7, out0, out1, out2, out3) \ macro