Searched refs:SUNXI_R_CPUCFG_BASE (Results 1 – 6 of 6) sorted by relevance
28 #define SUNXI_R_CPUCFG_CPUS_RST_REG (SUNXI_R_CPUCFG_BASE + 0x0000)29 #define SUNXI_POWERON_RST_REG(c) (SUNXI_R_CPUCFG_BASE + 0x0030 + (c) * 4)30 #define SUNXI_R_CPUCFG_SYS_RST_REG (SUNXI_R_CPUCFG_BASE + 0x0140)31 #define SUNXI_R_CPUCFG_SS_FLAG_REG (SUNXI_R_CPUCFG_BASE + 0x01a0)32 #define SUNXI_R_CPUCFG_CPU_ENTRY_REG (SUNXI_R_CPUCFG_BASE + 0x01a4)33 #define SUNXI_R_CPUCFG_SS_ENTRY_REG (SUNXI_R_CPUCFG_BASE + 0x01a8)34 #define SUNXI_R_CPUCFG_HP_FLAG_REG (SUNXI_R_CPUCFG_BASE + 0x01ac)
65 #define SUNXI_R_CPUCFG_BASE 0x01f01c00 macro
22 #define SUNXI_POWERON_RST_REG(c) (SUNXI_R_CPUCFG_BASE + 0x0040 + (c) * 4)23 #define SUNXI_POWEROFF_GATING_REG(c) (SUNXI_R_CPUCFG_BASE + 0x0044 + (c) * 4)24 #define SUNXI_CPU_POWER_CLAMP_REG(c, n) (SUNXI_R_CPUCFG_BASE + 0x0050 + \
56 #define SUNXI_R_CPUCFG_BASE 0x07000400 macro
174 if (!(mmio_read_32(SUNXI_R_CPUCFG_BASE) & BIT(0))) in sunxi_execute_arisc_code()193 mmio_setbits_32(SUNXI_R_CPUCFG_BASE, BIT(0)); in sunxi_execute_arisc_code()
260 mmio_setbits_32(SUNXI_R_CPUCFG_BASE, BIT(0)); in plat_setup_psci_ops()