| /external/llvm/lib/Target/AArch64/MCTargetDesc/ |
| D | AArch64AddressingModes.h | 45 SXTB, enumerator
64 case AArch64_AM::SXTB: return "sxtb"; in getShiftExtendName()
131 case 4: return AArch64_AM::SXTB; in getExtendType()
158 case AArch64_AM::SXTB: return 4; break; in getExtendEncoding()
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/MCTargetDesc/ |
| D | AArch64AddressingModes.h | 45 SXTB, enumerator
64 case AArch64_AM::SXTB: return "sxtb"; in getShiftExtendName()
131 case 4: return AArch64_AM::SXTB; in getExtendType()
158 case AArch64_AM::SXTB: return 4; break; in getExtendEncoding()
|
| /external/llvm-project/llvm/lib/Target/AArch64/MCTargetDesc/ |
| D | AArch64AddressingModes.h | 45 SXTB, enumerator
64 case AArch64_AM::SXTB: return "sxtb"; in getShiftExtendName()
131 case 4: return AArch64_AM::SXTB; in getExtendType()
158 case AArch64_AM::SXTB: return 4; break; in getExtendEncoding()
|
| /external/vixl/test/aarch32/config/ |
| D | cond-rd-operand-rn-t32.json | 54 "Sxtb", // SXTB{<c>}{<q>} {<Rd>}, <Rm> ; T1
55 // SXTB{<c>}{<q>} {<Rd>}, <Rm> {, ROR #<amount> } ; T2
|
| D | cond-rd-operand-rn-ror-amount-a32.json | 32 "Sxtb", // SXTB{<c>}{<q>} {<Rd>}, <Rm> {, ROR #<amount> } ; A1
|
| D | cond-rd-operand-rn-ror-amount-t32.json | 32 "Sxtb", // SXTB{<c>}{<q>} {<Rd>}, <Rm> {, ROR #<amount> } ; T2
|
| D | cond-rd-operand-rn-a32.json | 46 "Sxtb", // SXTB{<c>}{<q>} {<Rd>}, <Rm> {, ROR #<amount> } ; A1
|
| /external/llvm-project/llvm/test/CodeGen/ARM/GlobalISel/ |
| D | arm-instruction-select.mir | 142 ; CHECK: [[SXTB:%[0-9]+]]:gprnopc = SXTB [[COPY1]], 0, 14 /* CC::al */, $noreg
143 ; CHECK: $r0 = COPY [[SXTB]]
395 ; CHECK: [[SXTB:%[0-9]+]]:gprnopc = SXTB [[COPY2]], 0, 14 /* CC::al */, $noreg
396 ; CHECK: STRH [[SXTB]], [[COPY]], $noreg, 0, 14 /* CC::al */, $noreg :: (store 2)
|
| /external/llvm-project/llvm/test/MC/Disassembler/ARM/ |
| D | thumb1.txt | 503 # SXTB/SXTH
|
| D | invalid-armv7.txt | 353 # A8.6.223 SXTB
|
| /external/llvm/test/MC/Disassembler/ARM/ |
| D | thumb1.txt | 503 # SXTB/SXTH
|
| D | invalid-armv7.txt | 330 # A8.6.223 SXTB
|
| /external/llvm/lib/Target/AArch64/Utils/ |
| D | AArch64BaseInfo.h | 364 SXTB, enumerator
|
| /external/vixl/test/aarch64/ |
| D | test-assembler-aarch64.cc | 136 __ Add(sp, sp, Operand(x17, SXTB)); in TEST()
189 __ Mvn(x11, Operand(x2, SXTB, 1)); in TEST()
363 __ Mov(x24, Operand(x13, SXTB, 1)); in TEST()
417 __ Mov(w20, Operand(w11, SXTB, 1)); in TEST()
501 __ Orr(w10, w0, Operand(w1, SXTB)); in TEST()
595 __ Orn(w10, w0, Operand(w1, SXTB)); in TEST()
662 __ And(w10, w0, Operand(w1, SXTB)); in TEST()
808 __ Bic(w10, w0, Operand(w1, SXTB)); in TEST()
940 __ Eor(w10, w0, Operand(w1, SXTB)); in TEST()
1007 __ Eon(w10, w0, Operand(w1, SXTB)); in TEST()
[all …]
|
| D | test-disasm-aarch64.cc | 332 COMPARE(adds(w15, w16, Operand(w17, SXTB, 4)), "adds w15, w16, w17, sxtb #4"); in TEST()
333 COMPARE(add(x18, x19, Operand(x20, SXTB, 3)), "add x18, x19, w20, sxtb #3"); in TEST()
358 COMPARE(subs(w15, w16, Operand(w17, SXTB, 4)), "subs w15, w16, w17, sxtb #4"); in TEST()
359 COMPARE(sub(x18, x19, Operand(x20, SXTB, 3)), "sub x18, x19, w20, sxtb #3"); in TEST()
363 COMPARE(cmp(w0, Operand(w1, SXTB, 1)), "cmp w0, w1, sxtb #1"); in TEST()
2415 COMPARE_MACRO(Csel(x12, Operand(x13, LSL, 13), Operand(x14, SXTB), eq), in TEST()
2421 Operand(x14, SXTB), in TEST()
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/Utils/ |
| D | AArch64BaseInfo.h | 462 SXTB, enumerator
|
| /external/llvm-project/llvm/lib/Target/AArch64/Utils/ |
| D | AArch64BaseInfo.h | 462 SXTB, enumerator
|
| /external/llvm-project/llvm/test/CodeGen/AArch64/ |
| D | sve-intrinsics-conversion.ll | 8 ; SXTB
|
| /external/llvm-project/llvm/lib/Target/AArch64/ |
| D | AArch64SchedPredicates.td | 22 def CheckExtSXTB : CheckImmOperand_s<3, "AArch64_AM::SXTB">;
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/ |
| D | AArch64SchedPredicates.td | 22 def CheckExtSXTB : CheckImmOperand_s<3, "AArch64_AM::SXTB">;
|
| /external/llvm/test/MC/ARM/ |
| D | basic-thumb-instructions.s | 638 @ SXTB/SXTH
|
| /external/llvm-project/llvm/test/MC/ARM/ |
| D | basic-thumb-instructions.s | 638 @ SXTB/SXTH
|
| /external/llvm-project/llvm/lib/Target/ARM/ |
| D | ARMInstructionSelector.cpp | 303 STORE_OPCODE(SEXT8, SXTB); in OpcodeCache()
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/ |
| D | ARMInstructionSelector.cpp | 305 STORE_OPCODE(SEXT8, SXTB); in OpcodeCache()
|
| /external/pcre/dist2/src/sljit/ |
| D | sljitNativeARM_32.c | 131 #define SXTB 0xe6af0070 macro
1160 return push_inst(compiler, (op == SLJIT_MOV_U8 ? UXTB : SXTB) | RD(dst) | RM(src2)); in emit_single_op()
|