| /external/vixl/test/aarch32/ |
| D | test-disasm-a32.cc | 1538 COMPARE_BOTH(Sbc(r0, r1, -5), "adc r0, r1, #4\n"); in TEST()
1563 COMPARE_BOTH(Sbc(r0, r0, 0xabcd), in TEST()
1567 COMPARE_BOTH(Sbc(r0, r0, -0xabcd), in TEST()
1571 COMPARE_BOTH(Sbc(r0, r0, 0x1234abcd), in TEST()
1576 COMPARE_BOTH(Sbc(r0, r0, -0x1234abcd), in TEST()
3561 COMPARE_T32(Sbc(eq, r0, r0, r1), in TEST()
3565 COMPARE_T32(Sbc(eq, r0, r1, r2), in TEST()
4178 CHECK_T32_16(Sbc(DontCare, r7, r7, r6), "sbcs r7, r6\n"); in TEST()
4180 CHECK_T32_16_IT_BLOCK(Sbc(DontCare, eq, r7, r7, r6), in TEST()
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| D | test-simulator-cond-rd-rn-operand-rm-a32.cc | 132 M(Sbc) \
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| D | test-simulator-cond-rd-rn-operand-rm-t32.cc | 132 M(Sbc) \
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| D | test-simulator-cond-rd-rn-operand-const-a32.cc | 132 M(Sbc) \
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| D | test-simulator-cond-rd-rn-operand-rm-shift-amount-1to31-t32.cc | 132 M(Sbc) \
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| D | test-simulator-cond-rd-rn-operand-const-t32.cc | 132 M(Sbc) \
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| D | test-simulator-cond-rd-rn-operand-rm-shift-amount-1to31-a32.cc | 132 M(Sbc) \
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| D | test-simulator-cond-rd-rn-operand-rm-shift-amount-1to32-t32.cc | 132 M(Sbc) \
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| D | test-simulator-cond-rd-rn-operand-rm-shift-amount-1to32-a32.cc | 132 M(Sbc) \
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| D | test-simulator-cond-rd-rn-operand-rm-shift-rs-a32.cc | 132 M(Sbc) \
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| /external/swiftshader/third_party/subzero/src/ |
| D | IceInstARM32.h | 416 Sbc, enumerator
1015 using InstARM32Sbc = InstARM32ThreeAddrGPR<InstARM32::Sbc>;
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| D | IceInstARM32.cpp | 3498 template class InstARM32ThreeAddrGPR<InstARM32::Sbc>;
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| /external/vixl/src/aarch64/ |
| D | macro-assembler-aarch64.cc | 1825 void MacroAssembler::Sbc(const Register& rd, in Sbc() function in vixl::aarch64::MacroAssembler
1844 Sbc(rd, zr, operand); in Ngc()
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| D | macro-assembler-aarch64.h | 764 void Sbc(const Register& rd, const Register& rn, const Operand& operand);
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| /external/vixl/test/aarch64/ |
| D | test-assembler-aarch64.cc | 5233 __ Sbc(x7, x4, Operand(x3, LSR, 4)); in TEST() local
5239 __ Sbc(w12, w4, Operand(w3, LSR, 4)); in TEST() local
5248 __ Sbc(x20, x4, Operand(x3, LSR, 4)); in TEST() local
5254 __ Sbc(w25, w4, Operand(w3, LSR, 4)); in TEST() local
5302 __ Sbc(x12, x1, Operand(w2, UXTW, 4)); in TEST() local
5314 __ Sbc(x22, x1, Operand(w2, UXTW, 4)); in TEST() local
5399 __ Sbc(x9, x0, Operand(0x1234567890abcdef)); in TEST() local
5400 __ Sbc(w10, w0, Operand(0xffffffff)); in TEST() local
5409 __ Sbc(x20, x0, Operand(0x1234567890abcdef)); in TEST() local
5410 __ Sbc(w21, w0, Operand(0xffffffff)); in TEST() local
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| D | test-disasm-aarch64.cc | 2794 COMPARE_MACRO(Sbc(x0, x1, 0x4242), in TEST()
2797 COMPARE_MACRO(Sbc(x0, x0, 0x4242), in TEST()
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| /external/vixl/src/aarch32/ |
| D | macro-assembler-aarch32.h | 3347 void Sbc(Condition cond, Register rd, Register rn, const Operand& operand) { in Sbc() function
3361 void Sbc(Register rd, Register rn, const Operand& operand) { in Sbc() function
3362 Sbc(al, rd, rn, operand); in Sbc()
3364 void Sbc(FlagsUpdate flags, in Sbc() function
3371 Sbc(cond, rd, rn, operand); in Sbc()
3383 Sbc(cond, rd, rn, operand); in Sbc()
3388 void Sbc(FlagsUpdate flags, in Sbc() function
3392 Sbc(flags, al, rd, rn, operand); in Sbc()
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