Searched refs:SegmentReg (Results 1 – 9 of 9) sorted by relevance
| /external/swiftshader/third_party/subzero/src/ |
| D | IceInstX8632.cpp | 74 uint16_t Shift, SegmentRegisters SegmentReg, bool IsRebased) in X86OperandMem() argument
76 Shift(Shift), SegmentReg(SegmentReg), IsRebased(IsRebased) { in X86OperandMem()
145 if (SegmentReg != DefaultSegment) { in emit()
146 assert(SegmentReg >= 0 && SegmentReg < SegReg_NUM); in emit()
147 Str << "%" << X8632::Traits::InstSegmentRegNames[SegmentReg] << ":"; in emit()
187 if (SegmentReg != DefaultSegment) { in dump()
188 assert(SegmentReg >= 0 && SegmentReg < SegReg_NUM); in dump()
189 Str << X8632::Traits::InstSegmentRegNames[SegmentReg] << ":"; in dump()
250 if (SegmentReg != DefaultSegment) { in emitSegmentOverride()
251 assert(SegmentReg >= 0 && SegmentReg < SegReg_NUM); in emitSegmentOverride()
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| D | IceTargetLoweringX8632Traits.h | 786 SegmentRegisters SegmentReg = DefaultSegment,
789 Func, Ty, Base, Offset, Index, Shift, SegmentReg, IsRebased);
802 SegmentRegisters getSegmentRegister() const { return SegmentReg; }
818 Variable *Index, uint16_t Shift, SegmentRegisters SegmentReg,
825 const SegmentRegisters SegmentReg : 16;
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| D | IceTargetLoweringX86BaseImpl.h | 5982 static constexpr auto SegmentReg =
5986 NewAddr.Index, NewAddr.Shift, SegmentReg);
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| /external/llvm-project/llvm/lib/Target/X86/MCTargetDesc/ |
| D | X86AsmBackend.cpp | 390 unsigned SegmentReg = 0; in determinePaddingPrefix() local
393 SegmentReg = Inst.getOperand(MemoryOperand + X86::AddrSegmentReg).getReg(); in determinePaddingPrefix()
402 SegmentReg = Inst.getOperand(2).getReg(); in determinePaddingPrefix()
408 SegmentReg = Inst.getOperand(1).getReg(); in determinePaddingPrefix()
413 SegmentReg = Inst.getOperand(1).getReg(); in determinePaddingPrefix()
418 if (SegmentReg != 0) in determinePaddingPrefix()
419 return X86::getSegmentOverridePrefixForReg(SegmentReg); in determinePaddingPrefix()
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| /external/llvm/lib/Target/X86/ |
| D | X86MCInstLower.cpp | 780 unsigned Opc, BaseReg, ScaleVal, IndexReg, Displacement, SegmentReg; in EmitNop() local
781 Opc = IndexReg = Displacement = SegmentReg = 0; in EmitNop()
800 IndexReg = X86::RAX; SegmentReg = X86::CS; break; in EmitNop()
825 .addReg(SegmentReg), in EmitNop()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/ |
| D | X86MCInstLower.cpp | 1062 unsigned Opc, BaseReg, ScaleVal, IndexReg, Displacement, SegmentReg; in EmitNop() local
1063 IndexReg = Displacement = SegmentReg = 0; in EmitNop()
1121 SegmentReg = X86::CS; in EmitNop()
1145 .addReg(SegmentReg), in EmitNop()
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| /external/llvm-project/llvm/lib/Target/X86/ |
| D | X86MCInstLower.cpp | 1110 unsigned Opc, BaseReg, ScaleVal, IndexReg, Displacement, SegmentReg; in emitNop() local
1111 IndexReg = Displacement = SegmentReg = 0; in emitNop()
1169 SegmentReg = X86::CS; in emitNop()
1194 .addReg(SegmentReg), in emitNop()
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| /external/llvm-project/llvm/docs/ |
| D | CodeGenerator.rst | 2216 SegmentReg: Base + [1,2,4,8] * IndexReg + Disp32
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| /external/llvm/docs/ |
| D | CodeGenerator.rst | 2167 SegmentReg: Base + [1,2,4,8] * IndexReg + Disp32
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