| /external/capstone/arch/ARM/ |
| D | ARMAddressingModes.h | 115 static inline unsigned getSORegOpc(ARM_AM_ShiftOpc ShOp, unsigned Imm) in getSORegOpc() argument
117 return ShOp | (Imm << 3); in getSORegOpc()
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| D | ARMDisassembler.c | 1630 ARM_AM_ShiftOpc ShOp; in DecodeSORegMemOperand() local
1638 ShOp = ARM_AM_lsl; in DecodeSORegMemOperand()
1641 ShOp = ARM_AM_lsl; in DecodeSORegMemOperand()
1644 ShOp = ARM_AM_lsr; in DecodeSORegMemOperand()
1647 ShOp = ARM_AM_asr; in DecodeSORegMemOperand()
1650 ShOp = ARM_AM_ror; in DecodeSORegMemOperand()
1654 if (ShOp == ARM_AM_ror && imm == 0) in DecodeSORegMemOperand()
1655 ShOp = ARM_AM_rrx; in DecodeSORegMemOperand()
1662 shift = ARM_AM_getAM2Opc(ARM_AM_add, imm, ShOp, 0); in DecodeSORegMemOperand()
1664 shift = ARM_AM_getAM2Opc(ARM_AM_sub, imm, ShOp, 0); in DecodeSORegMemOperand()
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/MCTargetDesc/ |
| D | ARMAddressingModes.h | 112 inline unsigned getSORegOpc(ShiftOpc ShOp, unsigned Imm) { in getSORegOpc() argument
113 return ShOp | (Imm << 3); in getSORegOpc()
|
| D | ARMMCCodeEmitter.cpp | 1260 ARM_AM::ShiftOpc ShOp = ARM_AM::getAM2ShiftOpc(MO2.getImm()); in getLdStSORegOpValue() local
1261 unsigned SBits = getShiftOp(ShOp); in getLdStSORegOpValue()
1298 ARM_AM::ShiftOpc ShOp = ARM_AM::getAM2ShiftOpc(Imm); in getAddrMode2OffsetOpValue() local
1300 Binary |= getShiftOp(ShOp) << 5; // Shift type is bits [6:5] in getAddrMode2OffsetOpValue()
|
| /external/llvm-project/llvm/lib/Target/ARM/MCTargetDesc/ |
| D | ARMAddressingModes.h | 112 inline unsigned getSORegOpc(ShiftOpc ShOp, unsigned Imm) { in getSORegOpc() argument
113 return ShOp | (Imm << 3); in getSORegOpc()
|
| D | ARMMCCodeEmitter.cpp | 1252 ARM_AM::ShiftOpc ShOp = ARM_AM::getAM2ShiftOpc(MO2.getImm()); in getLdStSORegOpValue() local
1253 unsigned SBits = getShiftOp(ShOp); in getLdStSORegOpValue()
1290 ARM_AM::ShiftOpc ShOp = ARM_AM::getAM2ShiftOpc(Imm); in getAddrMode2OffsetOpValue() local
1292 Binary |= getShiftOp(ShOp) << 5; // Shift type is bits [6:5] in getAddrMode2OffsetOpValue()
|
| /external/llvm/lib/Target/ARM/MCTargetDesc/ |
| D | ARMAddressingModes.h | 112 static inline unsigned getSORegOpc(ShiftOpc ShOp, unsigned Imm) { in getSORegOpc() argument
113 return ShOp | (Imm << 3); in getSORegOpc()
|
| D | ARMMCCodeEmitter.cpp | 1076 ARM_AM::ShiftOpc ShOp = ARM_AM::getAM2ShiftOpc(MO2.getImm()); in getLdStSORegOpValue() local
1077 unsigned SBits = getShiftOp(ShOp); in getLdStSORegOpValue()
1114 ARM_AM::ShiftOpc ShOp = ARM_AM::getAM2ShiftOpc(Imm); in getAddrMode2OffsetOpValue() local
1116 Binary |= getShiftOp(ShOp) << 5; // Shift type is bits [6:5] in getAddrMode2OffsetOpValue()
|
| /external/llvm/lib/Target/AArch64/AsmParser/ |
| D | AArch64AsmParser.cpp | 1761 CreateShiftExtend(AArch64_AM::ShiftExtendType ShOp, unsigned Val, in CreateShiftExtend() argument
1764 Op->ShiftExtend.Type = ShOp; in CreateShiftExtend()
2382 AArch64_AM::ShiftExtendType ShOp = in tryParseOptionalShiftExtend() local
2399 if (ShOp == AArch64_AM::InvalidShiftExtend) in tryParseOptionalShiftExtend()
2407 if (ShOp == AArch64_AM::LSL || ShOp == AArch64_AM::LSR || in tryParseOptionalShiftExtend()
2408 ShOp == AArch64_AM::ASR || ShOp == AArch64_AM::ROR || in tryParseOptionalShiftExtend()
2409 ShOp == AArch64_AM::MSL) { in tryParseOptionalShiftExtend()
2418 AArch64Operand::CreateShiftExtend(ShOp, 0, false, S, E, getContext())); in tryParseOptionalShiftExtend()
2445 ShOp, MCE->getValue(), true, S, E, getContext())); in tryParseOptionalShiftExtend()
|
| /external/llvm/lib/Target/ARM/ |
| D | ARMInstrNEON.td | 2572 ValueType Ty, SDNode ShOp>
2577 (Ty (ShOp (Ty DPR:$Vn),
2584 string OpcodeStr, string Dt, ValueType Ty, SDNode ShOp>
2589 (Ty (ShOp (Ty DPR:$Vn),
2620 ValueType ResTy, ValueType OpTy, SDNode ShOp>
2625 (ResTy (ShOp (ResTy QPR:$Vn),
2633 ValueType ResTy, ValueType OpTy, SDNode ShOp>
2638 (ResTy (ShOp (ResTy QPR:$Vn),
2780 ValueType Ty, SDPatternOperator MulOp, SDPatternOperator ShOp>
2787 (Ty (ShOp (Ty DPR:$src1),
[all …]
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/AsmParser/ |
| D | AArch64AsmParser.cpp | 1989 CreateShiftExtend(AArch64_AM::ShiftExtendType ShOp, unsigned Val, in CreateShiftExtend() argument
1992 Op->ShiftExtend.Type = ShOp; in CreateShiftExtend()
2743 AArch64_AM::ShiftExtendType ShOp = in tryParseOptionalShiftExtend() local
2760 if (ShOp == AArch64_AM::InvalidShiftExtend) in tryParseOptionalShiftExtend()
2769 if (ShOp == AArch64_AM::LSL || ShOp == AArch64_AM::LSR || in tryParseOptionalShiftExtend()
2770 ShOp == AArch64_AM::ASR || ShOp == AArch64_AM::ROR || in tryParseOptionalShiftExtend()
2771 ShOp == AArch64_AM::MSL) { in tryParseOptionalShiftExtend()
2780 AArch64Operand::CreateShiftExtend(ShOp, 0, false, S, E, getContext())); in tryParseOptionalShiftExtend()
2806 ShOp, MCE->getValue(), true, S, E, getContext())); in tryParseOptionalShiftExtend()
|
| /external/llvm-project/llvm/lib/Target/AArch64/AsmParser/ |
| D | AArch64AsmParser.cpp | 2034 CreateShiftExtend(AArch64_AM::ShiftExtendType ShOp, unsigned Val, in CreateShiftExtend() argument
2037 Op->ShiftExtend.Type = ShOp; in CreateShiftExtend()
2794 AArch64_AM::ShiftExtendType ShOp = in tryParseOptionalShiftExtend() local
2811 if (ShOp == AArch64_AM::InvalidShiftExtend) in tryParseOptionalShiftExtend()
2820 if (ShOp == AArch64_AM::LSL || ShOp == AArch64_AM::LSR || in tryParseOptionalShiftExtend()
2821 ShOp == AArch64_AM::ASR || ShOp == AArch64_AM::ROR || in tryParseOptionalShiftExtend()
2822 ShOp == AArch64_AM::MSL) { in tryParseOptionalShiftExtend()
2831 AArch64Operand::CreateShiftExtend(ShOp, 0, false, S, E, getContext())); in tryParseOptionalShiftExtend()
2857 ShOp, MCE->getValue(), true, S, E, getContext())); in tryParseOptionalShiftExtend()
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/ |
| D | ARMInstrNEON.td | 2656 ValueType Ty, SDNode ShOp>
2661 (Ty (ShOp (Ty DPR:$Vn),
2668 string OpcodeStr, string Dt, ValueType Ty, SDNode ShOp>
2673 (Ty (ShOp (Ty DPR:$Vn),
2704 ValueType ResTy, ValueType OpTy, SDNode ShOp>
2709 (ResTy (ShOp (ResTy QPR:$Vn),
2717 ValueType ResTy, ValueType OpTy, SDNode ShOp>
2722 (ResTy (ShOp (ResTy QPR:$Vn),
2864 ValueType Ty, SDPatternOperator MulOp, SDPatternOperator ShOp>
2871 (Ty (ShOp (Ty DPR:$src1),
[all …]
|
| /external/llvm-project/llvm/lib/Target/ARM/ |
| D | ARMInstrNEON.td | 2587 ValueType Ty, SDNode ShOp>
2592 (Ty (ShOp (Ty DPR:$Vn),
2599 string OpcodeStr, string Dt, ValueType Ty, SDNode ShOp>
2604 (Ty (ShOp (Ty DPR:$Vn),
2635 ValueType ResTy, ValueType OpTy, SDNode ShOp>
2640 (ResTy (ShOp (ResTy QPR:$Vn),
2648 ValueType ResTy, ValueType OpTy, SDNode ShOp>
2653 (ResTy (ShOp (ResTy QPR:$Vn),
2795 ValueType Ty, SDPatternOperator MulOp, SDPatternOperator ShOp>
2802 (Ty (ShOp (Ty DPR:$src1),
[all …]
|
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | LegalizeVectorTypes.cpp | 2490 SDValue ShOp = N->getOperand(1); in WidenVecRes_POWI() local
2491 return DAG.getNode(N->getOpcode(), SDLoc(N), WidenVT, InOp, ShOp); in WidenVecRes_POWI()
2497 SDValue ShOp = N->getOperand(1); in WidenVecRes_Shift() local
2499 EVT ShVT = ShOp.getValueType(); in WidenVecRes_Shift()
2501 ShOp = GetWidenedVector(ShOp); in WidenVecRes_Shift()
2502 ShVT = ShOp.getValueType(); in WidenVecRes_Shift()
2508 ShOp = ModifyToType(ShOp, ShWidenVT); in WidenVecRes_Shift()
2510 return DAG.getNode(N->getOpcode(), SDLoc(N), WidenVT, InOp, ShOp); in WidenVecRes_Shift()
|
| D | DAGCombiner.cpp | 2806 SDValue ShOp = N0->getOperand(1); in SimplifyBinOpWithSameOpcodeHands() local
2810 if (N->getOpcode() == ISD::XOR && !ShOp.isUndef()) { in SimplifyBinOpWithSameOpcodeHands()
2812 ShOp = DAG.getConstant(0, SDLoc(N), VT); in SimplifyBinOpWithSameOpcodeHands()
2814 ShOp = SDValue(); in SimplifyBinOpWithSameOpcodeHands()
2820 if (N0.getOperand(1) == N1.getOperand(1) && ShOp.getNode()) { in SimplifyBinOpWithSameOpcodeHands()
2824 return DAG.getVectorShuffle(VT, SDLoc(N), NewNode, ShOp, in SimplifyBinOpWithSameOpcodeHands()
2830 ShOp = N0->getOperand(0); in SimplifyBinOpWithSameOpcodeHands()
2831 if (N->getOpcode() == ISD::XOR && !ShOp.isUndef()) { in SimplifyBinOpWithSameOpcodeHands()
2833 ShOp = DAG.getConstant(0, SDLoc(N), VT); in SimplifyBinOpWithSameOpcodeHands()
2835 ShOp = SDValue(); in SimplifyBinOpWithSameOpcodeHands()
[all …]
|
| /external/llvm/lib/Target/ARM/Disassembler/ |
| D | ARMDisassembler.cpp | 1586 ARM_AM::ShiftOpc ShOp = ARM_AM::lsl; in DecodeSORegMemOperand() local
1589 ShOp = ARM_AM::lsl; in DecodeSORegMemOperand()
1592 ShOp = ARM_AM::lsr; in DecodeSORegMemOperand()
1595 ShOp = ARM_AM::asr; in DecodeSORegMemOperand()
1598 ShOp = ARM_AM::ror; in DecodeSORegMemOperand()
1602 if (ShOp == ARM_AM::ror && imm == 0) in DecodeSORegMemOperand()
1603 ShOp = ARM_AM::rrx; in DecodeSORegMemOperand()
1611 shift = ARM_AM::getAM2Opc(ARM_AM::add, imm, ShOp); in DecodeSORegMemOperand()
1613 shift = ARM_AM::getAM2Opc(ARM_AM::sub, imm, ShOp); in DecodeSORegMemOperand()
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/SelectionDAG/ |
| D | LegalizeVectorTypes.cpp | 3410 SDValue ShOp = N->getOperand(1); in WidenVecRes_POWI() local
3411 return DAG.getNode(N->getOpcode(), SDLoc(N), WidenVT, InOp, ShOp); in WidenVecRes_POWI()
3417 SDValue ShOp = N->getOperand(1); in WidenVecRes_Shift() local
3419 EVT ShVT = ShOp.getValueType(); in WidenVecRes_Shift()
3421 ShOp = GetWidenedVector(ShOp); in WidenVecRes_Shift()
3422 ShVT = ShOp.getValueType(); in WidenVecRes_Shift()
3428 ShOp = ModifyToType(ShOp, ShWidenVT); in WidenVecRes_Shift()
3430 return DAG.getNode(N->getOpcode(), SDLoc(N), WidenVT, InOp, ShOp); in WidenVecRes_Shift()
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| D | DAGCombiner.cpp | 4494 SDValue ShOp = N0.getOperand(1); in hoistLogicOpWithSameOpcodeHands() local
4495 if (LogicOpcode == ISD::XOR && !ShOp.isUndef()) in hoistLogicOpWithSameOpcodeHands()
4496 ShOp = tryFoldToZero(DL, TLI, VT, DAG, LegalOperations); in hoistLogicOpWithSameOpcodeHands()
4499 if (N0.getOperand(1) == N1.getOperand(1) && ShOp.getNode()) { in hoistLogicOpWithSameOpcodeHands()
4502 return DAG.getVectorShuffle(VT, DL, Logic, ShOp, SVN0->getMask()); in hoistLogicOpWithSameOpcodeHands()
4507 ShOp = N0.getOperand(0); in hoistLogicOpWithSameOpcodeHands()
4508 if (LogicOpcode == ISD::XOR && !ShOp.isUndef()) in hoistLogicOpWithSameOpcodeHands()
4509 ShOp = tryFoldToZero(DL, TLI, VT, DAG, LegalOperations); in hoistLogicOpWithSameOpcodeHands()
4512 if (N0.getOperand(0) == N1.getOperand(0) && ShOp.getNode()) { in hoistLogicOpWithSameOpcodeHands()
4515 return DAG.getVectorShuffle(VT, DL, ShOp, Logic, SVN0->getMask()); in hoistLogicOpWithSameOpcodeHands()
|
| /external/llvm-project/llvm/lib/Target/ARM/Disassembler/ |
| D | ARMDisassembler.cpp | 1959 ARM_AM::ShiftOpc ShOp = ARM_AM::lsl; in DecodeSORegMemOperand() local
1962 ShOp = ARM_AM::lsl; in DecodeSORegMemOperand()
1965 ShOp = ARM_AM::lsr; in DecodeSORegMemOperand()
1968 ShOp = ARM_AM::asr; in DecodeSORegMemOperand()
1971 ShOp = ARM_AM::ror; in DecodeSORegMemOperand()
1975 if (ShOp == ARM_AM::ror && imm == 0) in DecodeSORegMemOperand()
1976 ShOp = ARM_AM::rrx; in DecodeSORegMemOperand()
1984 shift = ARM_AM::getAM2Opc(ARM_AM::add, imm, ShOp); in DecodeSORegMemOperand()
1986 shift = ARM_AM::getAM2Opc(ARM_AM::sub, imm, ShOp); in DecodeSORegMemOperand()
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/Disassembler/ |
| D | ARMDisassembler.cpp | 1938 ARM_AM::ShiftOpc ShOp = ARM_AM::lsl; in DecodeSORegMemOperand() local
1941 ShOp = ARM_AM::lsl; in DecodeSORegMemOperand()
1944 ShOp = ARM_AM::lsr; in DecodeSORegMemOperand()
1947 ShOp = ARM_AM::asr; in DecodeSORegMemOperand()
1950 ShOp = ARM_AM::ror; in DecodeSORegMemOperand()
1954 if (ShOp == ARM_AM::ror && imm == 0) in DecodeSORegMemOperand()
1955 ShOp = ARM_AM::rrx; in DecodeSORegMemOperand()
1963 shift = ARM_AM::getAM2Opc(ARM_AM::add, imm, ShOp); in DecodeSORegMemOperand()
1965 shift = ARM_AM::getAM2Opc(ARM_AM::sub, imm, ShOp); in DecodeSORegMemOperand()
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| /external/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| D | DAGCombiner.cpp | 4767 SDValue ShOp = N0.getOperand(1); in hoistLogicOpWithSameOpcodeHands() local
4768 if (LogicOpcode == ISD::XOR && !ShOp.isUndef()) in hoistLogicOpWithSameOpcodeHands()
4769 ShOp = tryFoldToZero(DL, TLI, VT, DAG, LegalOperations); in hoistLogicOpWithSameOpcodeHands()
4772 if (N0.getOperand(1) == N1.getOperand(1) && ShOp.getNode()) { in hoistLogicOpWithSameOpcodeHands()
4775 return DAG.getVectorShuffle(VT, DL, Logic, ShOp, SVN0->getMask()); in hoistLogicOpWithSameOpcodeHands()
4780 ShOp = N0.getOperand(0); in hoistLogicOpWithSameOpcodeHands()
4781 if (LogicOpcode == ISD::XOR && !ShOp.isUndef()) in hoistLogicOpWithSameOpcodeHands()
4782 ShOp = tryFoldToZero(DL, TLI, VT, DAG, LegalOperations); in hoistLogicOpWithSameOpcodeHands()
4785 if (N0.getOperand(0) == N1.getOperand(0) && ShOp.getNode()) { in hoistLogicOpWithSameOpcodeHands()
4788 return DAG.getVectorShuffle(VT, DL, ShOp, Logic, SVN0->getMask()); in hoistLogicOpWithSameOpcodeHands()
|
| D | LegalizeVectorTypes.cpp | 3573 SDValue ShOp = N->getOperand(1); in WidenVecRes_POWI() local
3574 return DAG.getNode(N->getOpcode(), SDLoc(N), WidenVT, InOp, ShOp); in WidenVecRes_POWI()
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/ |
| D | HexagonPatterns.td | 1229 class OpshIRI_pat<InstHexagon MI, PatFrag Op, PatFrag ShOp,
1231 : Pat<(Op anyimm:$u8, (ShOp RegPred:$Rs, ImmPred:$U5)),
|
| /external/llvm-project/llvm/lib/Target/Hexagon/ |
| D | HexagonPatterns.td | 1262 class OpshIRI_pat<InstHexagon MI, PatFrag Op, PatFrag ShOp,
1264 : Pat<(Op anyimm:$u8, (ShOp RegPred:$Rs, ImmPred:$U5)),
|