Searched refs:Shift1 (Results 1 – 8 of 8) sorted by relevance
| /external/llvm-project/llvm/lib/Target/AMDGPU/ |
| D | AMDGPUInstructionSelector.cpp | 650 bool Shift1 = mi_match( in selectG_BUILD_VECTOR_TRUNC() local
654 if (Shift0 && Shift1) { in selectG_BUILD_VECTOR_TRUNC()
658 } else if (Shift1) { in selectG_BUILD_VECTOR_TRUNC()
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| /external/llvm-project/llvm/lib/CodeGen/GlobalISel/ |
| D | CombinerHelper.cpp | 1716 Register Shift1 = in applyShiftOfShiftedLogic() local
1726 Builder.buildInstr(MatchInfo.Logic->getOpcode(), {Dest}, {Shift1, Shift2}); in applyShiftOfShiftedLogic()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/PowerPC/ |
| D | PPCInstrInfo.td | 4986 def Shift1 {
4992 dag Bit = (OR (AND Shift1.Right, MaskValues.Lo1),
4993 (AND Shift1.Left, MaskValues.Hi1));
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| /external/llvm-project/llvm/lib/Target/PowerPC/ |
| D | PPCInstrInfo.td | 5187 def Shift1 {
5193 dag Bit = (OR (AND Shift1.Right, MaskValues.Lo1),
5194 (AND Shift1.Left, MaskValues.Hi1));
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| /external/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| D | DAGCombiner.cpp | 6040 SDValue Shift1 = N1.getOperand(0); in matchBSwapHWordOrAndAnd() local
6041 if (Shift0.getOpcode() != ISD::SHL || Shift1.getOpcode() != ISD::SRL) in matchBSwapHWordOrAndAnd()
6044 ConstantSDNode *ShiftAmt1 = isConstOrConstSplat(Shift1.getOperand(1)); in matchBSwapHWordOrAndAnd()
6049 if (Shift0.getOperand(0) != Shift1.getOperand(0)) in matchBSwapHWordOrAndAnd()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/ |
| D | X86ISelLowering.cpp | 26727 SDValue Shift1 = getTargetVShiftByConstNode(X86OpcI, dl, VT, R, in LowerShift() local
26731 return DAG.getVectorShuffle(VT, dl, Shift1, Shift2, ShuffleMask); in LowerShift()
39096 SDValue Shift1 = DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0), in combineMulSpecial() local
39100 return DAG.getNode(ISD::ADD, DL, VT, Shift1, Shift2); in combineMulSpecial()
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| /external/llvm-project/llvm/lib/Target/X86/ |
| D | X86ISelLowering.cpp | 27814 SDValue Shift1 = getTargetVShiftByConstNode(X86OpcI, dl, VT, R, in LowerShift() local
27818 return DAG.getVectorShuffle(VT, dl, Shift1, Shift2, ShuffleMask); in LowerShift()
42124 SDValue Shift1 = DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0), in combineMulSpecial() local
42128 return DAG.getNode(ISD::ADD, DL, VT, Shift1, Shift2); in combineMulSpecial()
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| /external/llvm/lib/Target/X86/ |
| D | X86ISelLowering.cpp | 20166 SDValue Shift1 = DAG.getNode(Op->getOpcode(), dl, VT, R, Splat1); in LowerShift() local
20172 SDValue BitCast1 = DAG.getBitcast(CastVT, Shift1); in LowerShift()
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