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Searched refs:Shift2 (Results 1 – 21 of 21) sorted by relevance

/external/llvm-project/llvm/test/tools/llvm-readobj/ELF/
Dgnuhash.test33 Shift2: 0x2
92 Shift2: 0x0
140 Shift2: 0x0
192 Shift2: 0x0
261 Shift2: 0x0
Dhash-histogram.test45 Shift2: 0x0
239 Shift2: 0x0
286 Shift2: 0x0
350 Shift2: 0x0
395 Shift2: 0x0
Dhash-symbols.test62 Shift2: 0x0
220 Shift2: 0x0
492 Shift2: 0x2
616 Shift2: 0x0
672 Shift2: 0x0
/external/llvm-project/llvm/lib/Target/Mips/
DMipsISelLowering.h462 SDValue Shift2 = DAG.getNode(ISD::SHL, DL, Ty, Add, Cst); in getAddrNonPICSym64() local
464 return DAG.getNode(ISD::ADD, DL, Ty, Shift2, in getAddrNonPICSym64()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/
DMipsISelLowering.h476 SDValue Shift2 = DAG.getNode(ISD::SHL, DL, Ty, Add, Cst); in getAddrNonPICSym64() local
478 return DAG.getNode(ISD::ADD, DL, Ty, Shift2, in getAddrNonPICSym64()
/external/llvm-project/llvm/include/llvm/CodeGen/GlobalISel/
DCombinerHelper.h64 MachineInstr *Shift2; member
/external/llvm-project/llvm/lib/CodeGen/GlobalISel/
DCombinerHelper.cpp1684 MatchInfo.Shift2 = LogicMIOp1; in matchShiftOfShiftedLogic()
1687 MatchInfo.Shift2 = LogicMIOp2; in matchShiftOfShiftedLogic()
1715 Register Shift1Base = MatchInfo.Shift2->getOperand(1).getReg(); in applyShiftOfShiftedLogic()
1720 Register Shift2 = Builder in applyShiftOfShiftedLogic() local
1726 Builder.buildInstr(MatchInfo.Logic->getOpcode(), {Dest}, {Shift1, Shift2}); in applyShiftOfShiftedLogic()
1729 MatchInfo.Shift2->eraseFromParent(); in applyShiftOfShiftedLogic()
/external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/ObjectYAML/
DELFYAML.h301 llvm::yaml::Hex32 Shift2; member
/external/llvm-project/llvm/include/llvm/ObjectYAML/
DELFYAML.h360 llvm::yaml::Hex32 Shift2; member
/external/llvm-project/lld/ELF/
DSyntheticSections.h642 enum { Shift2 = 26 }; enumerator
DSyntheticSections.cpp2350 write32(buf + 12, Shift2); in writeTo()
2374 val |= uint64_t(1) << ((sym.hash >> Shift2) % c); in writeBloomFilter()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/ObjectYAML/
DELFYAML.cpp1502 IO.mapRequired("Shift2", E.Shift2); in mapping()
DELFEmitter.cpp1288 support::endian::write<uint32_t>(OS, Section.Header->Shift2, in writeSectionContent()
/external/llvm-project/llvm/tools/obj2yaml/
Delf2yaml.cpp1275 Header.Shift2 = Data.getU32(Cur); in dumpGnuHashSection()
/external/llvm-project/llvm/lib/ObjectYAML/
DELFYAML.cpp1561 IO.mapRequired("Shift2", E.Shift2); in mapping()
DELFEmitter.cpp1728 CBA.write<uint32_t>(Section.Header->Shift2, ELFT::TargetEndianness); in writeSectionContent()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/PowerPC/
DPPCInstrInfo.td4996 def Shift2 {
5002 dag Bits = (OR (AND Shift2.Right, MaskValues.Lo2),
5003 (AND Shift2.Left, MaskValues.Hi2));
/external/llvm-project/llvm/lib/Target/PowerPC/
DPPCInstrInfo.td5197 def Shift2 {
5203 dag Bits = (OR (AND Shift2.Right, MaskValues.Lo2),
5204 (AND Shift2.Left, MaskValues.Hi2));
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/
DX86ISelLowering.cpp26729 SDValue Shift2 = getTargetVShiftByConstNode(X86OpcI, dl, VT, R, in LowerShift() local
26731 return DAG.getVectorShuffle(VT, dl, Shift1, Shift2, ShuffleMask); in LowerShift()
39098 SDValue Shift2 = DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0), in combineMulSpecial() local
39100 return DAG.getNode(ISD::ADD, DL, VT, Shift1, Shift2); in combineMulSpecial()
/external/llvm-project/llvm/lib/Target/X86/
DX86ISelLowering.cpp27816 SDValue Shift2 = getTargetVShiftByConstNode(X86OpcI, dl, VT, R, in LowerShift() local
27818 return DAG.getVectorShuffle(VT, dl, Shift1, Shift2, ShuffleMask); in LowerShift()
42126 SDValue Shift2 = DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0), in combineMulSpecial() local
42128 return DAG.getNode(ISD::ADD, DL, VT, Shift1, Shift2); in combineMulSpecial()
/external/llvm/lib/Target/X86/
DX86ISelLowering.cpp20169 SDValue Shift2 = DAG.getNode(Op->getOpcode(), dl, VT, R, Splat2); in LowerShift() local
20173 SDValue BitCast2 = DAG.getBitcast(CastVT, Shift2); in LowerShift()