| /external/llvm-project/llvm/lib/Target/RISCV/Utils/ |
| D | RISCVMatInt.cpp | 66 int ShiftAmount = 12 + findFirstSet((uint64_t)Hi52); in generateInstSeq() local
67 Hi52 = SignExtend64(Hi52 >> (ShiftAmount - 12), 64 - ShiftAmount); in generateInstSeq()
71 Res.push_back(Inst(RISCV::SLLI, ShiftAmount)); in generateInstSeq()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/RISCV/Utils/ |
| D | RISCVMatInt.cpp | 68 int ShiftAmount = 12 + findFirstSet((uint64_t)Hi52); in generateInstSeq() local
69 Hi52 = SignExtend64(Hi52 >> (ShiftAmount - 12), 64 - ShiftAmount); in generateInstSeq()
73 Res.push_back(Inst(RISCV::SLLI, ShiftAmount)); in generateInstSeq()
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| /external/swiftshader/third_party/subzero/src/ |
| D | IceTargetLoweringMIPS32.cpp | 2566 int64_t ShiftAmount = Const->getValue(); in lowerInt64Arithmetic() local
2567 if (ShiftAmount == 1) { in lowerInt64Arithmetic()
2573 } else if (ShiftAmount < INT32_BITS) { in lowerInt64Arithmetic()
2575 _srl(T1, Src0LoR, INT32_BITS - ShiftAmount); in lowerInt64Arithmetic()
2576 _sll(T2, Src0HiR, ShiftAmount); in lowerInt64Arithmetic()
2578 _sll(T_Lo, Src0LoR, ShiftAmount); in lowerInt64Arithmetic()
2579 } else if (ShiftAmount == INT32_BITS) { in lowerInt64Arithmetic()
2582 } else if (ShiftAmount > INT32_BITS && ShiftAmount < 64) { in lowerInt64Arithmetic()
2583 _sll(T_Hi, Src0LoR, ShiftAmount - INT32_BITS); in lowerInt64Arithmetic()
2625 int64_t ShiftAmount = Const->getValue(); in lowerInt64Arithmetic() local
[all …]
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/RISCV/ |
| D | RISCVFrameLowering.cpp | 222 unsigned ShiftAmount = countTrailingZeros(MaxAlignment); in emitPrologue() local
227 .addImm(ShiftAmount); in emitPrologue()
230 .addImm(ShiftAmount); in emitPrologue()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/ |
| D | MipsSEISelDAGToDAG.h | 48 unsigned ShiftAmount) const;
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| D | MipsSEISelDAGToDAG.cpp | 283 unsigned ShiftAmount = 0) const { in selectAddrFrameIndexOffset() argument
286 if (isIntN(OffsetBits + ShiftAmount, CN->getSExtValue())) { in selectAddrFrameIndexOffset()
297 const Align Alignment(1ULL << ShiftAmount); in selectAddrFrameIndexOffset()
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| D | MipsTargetStreamer.h | 142 void emitDSLL(unsigned DstReg, unsigned SrcReg, int16_t ShiftAmount,
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| /external/llvm-project/llvm/lib/Target/Mips/ |
| D | MipsSEISelDAGToDAG.h | 48 unsigned ShiftAmount) const;
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| /external/llvm-project/llvm/lib/Target/Mips/MCTargetDesc/ |
| D | MipsTargetStreamer.cpp | 268 int16_t ShiftAmount, SMLoc IDLoc, in emitDSLL() argument
270 if (ShiftAmount >= 32) { in emitDSLL()
271 emitRRI(Mips::DSLL32, DstReg, SrcReg, ShiftAmount - 32, IDLoc, STI); in emitDSLL()
275 emitRRI(Mips::DSLL, DstReg, SrcReg, ShiftAmount, IDLoc, STI); in emitDSLL()
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| D | MipsMCCodeEmitter.h | 188 template <unsigned ShiftAmount = 0>
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/MCTargetDesc/ |
| D | MipsTargetStreamer.cpp | 265 int16_t ShiftAmount, SMLoc IDLoc, in emitDSLL() argument
267 if (ShiftAmount >= 32) { in emitDSLL()
268 emitRRI(Mips::DSLL32, DstReg, SrcReg, ShiftAmount - 32, IDLoc, STI); in emitDSLL()
272 emitRRI(Mips::DSLL, DstReg, SrcReg, ShiftAmount, IDLoc, STI); in emitDSLL()
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| D | MipsMCCodeEmitter.h | 188 template <unsigned ShiftAmount = 0>
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| /external/llvm/lib/Target/Mips/MCTargetDesc/ |
| D | MipsTargetStreamer.cpp | 200 int16_t ShiftAmount, SMLoc IDLoc, in emitDSLL() argument
202 if (ShiftAmount >= 32) { in emitDSLL()
203 emitRRI(Mips::DSLL32, DstReg, SrcReg, ShiftAmount - 32, IDLoc, STI); in emitDSLL()
207 emitRRI(Mips::DSLL, DstReg, SrcReg, ShiftAmount, IDLoc, STI); in emitDSLL()
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| D | MipsMCCodeEmitter.h | 185 template <unsigned ShiftAmount = 0>
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| /external/llvm-project/llvm/lib/Target/RISCV/ |
| D | RISCVFrameLowering.cpp | 477 unsigned ShiftAmount = Log2(MaxAlignment); in emitPrologue() local
482 .addImm(ShiftAmount); in emitPrologue()
485 .addImm(ShiftAmount); in emitPrologue()
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| /external/llvm/lib/Target/AArch64/AsmParser/ |
| D | AArch64AsmParser.cpp | 199 unsigned ShiftAmount; member
351 return ShiftedImm.ShiftAmount; in getShiftedImmShift()
704 unsigned Shift = ShiftedImm.ShiftAmount; in isAddSubImm()
742 unsigned Shift = ShiftedImm.ShiftAmount; in isAddSubImmNeg()
1271 unsigned ShiftAmt = isShiftedImm() ? ShiftedImm.ShiftAmount : 0; in addAddSubImmNegOperands()
1667 unsigned ShiftAmount, in CreateShiftedImm() argument
1672 Op->ShiftedImm.ShiftAmount = ShiftAmount; in CreateShiftedImm()
2274 uint64_t ShiftAmount = 0; in tryParseAddSubImm() local
2280 ShiftAmount = 12; in tryParseAddSubImm()
2284 Operands.push_back(AArch64Operand::CreateShiftedImm(Imm, ShiftAmount, S, E, in tryParseAddSubImm()
[all …]
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/MSP430/ |
| D | MSP430ISelLowering.cpp | 970 uint64_t ShiftAmount = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue(); in LowerShifts() local
975 if (ShiftAmount >= 8) { in LowerShifts()
995 ShiftAmount -= 8; in LowerShifts()
998 if (Opc == ISD::SRL && ShiftAmount) { in LowerShifts()
1002 ShiftAmount -= 1; in LowerShifts()
1005 while (ShiftAmount--) in LowerShifts()
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| /external/llvm-project/llvm/lib/Target/MSP430/ |
| D | MSP430ISelLowering.cpp | 967 uint64_t ShiftAmount = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue(); in LowerShifts() local
972 if (ShiftAmount >= 8) { in LowerShifts()
992 ShiftAmount -= 8; in LowerShifts()
995 if (Opc == ISD::SRL && ShiftAmount) { in LowerShifts()
999 ShiftAmount -= 1; in LowerShifts()
1002 while (ShiftAmount--) in LowerShifts()
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| /external/llvm-project/llvm/lib/Target/AVR/ |
| D | AVRISelLowering.cpp | 312 uint64_t ShiftAmount = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue(); in LowerShifts() local
321 ShiftAmount = ShiftAmount % VT.getSizeInBits(); in LowerShifts()
325 ShiftAmount = ShiftAmount % VT.getSizeInBits(); in LowerShifts()
337 while (ShiftAmount--) { in LowerShifts()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/AsmParser/ |
| D | AArch64AsmParser.cpp | 354 unsigned ShiftAmount; member
511 return ShiftedImm.ShiftAmount; in getShiftedImmShift()
797 unsigned Shift = ShiftedImm.ShiftAmount; in isAddSubImm()
1817 unsigned ShiftAmount = 0, in CreateReg() argument
1825 Op->Reg.ShiftExtend.Amount = ShiftAmount; in CreateReg()
1836 unsigned ShiftAmount = 0, in CreateVectorReg() argument
1841 auto Op = CreateReg(RegNum, Kind, S, E, Ctx, EqualsReg, ExtTy, ShiftAmount, in CreateVectorReg()
1881 unsigned ShiftAmount, in CreateShiftedImm() argument
1886 Op->ShiftedImm.ShiftAmount = ShiftAmount; in CreateShiftedImm()
2649 int64_t ShiftAmount = Parser.getTok().getIntVal(); in tryParseImmWithOptionalShift() local
[all …]
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| /external/llvm-project/llvm/lib/Target/AArch64/AsmParser/ |
| D | AArch64AsmParser.cpp | 388 unsigned ShiftAmount; member
545 return ShiftedImm.ShiftAmount; in getShiftedImmShift()
832 unsigned Shift = ShiftedImm.ShiftAmount; in isAddSubImm()
1862 unsigned ShiftAmount = 0, in CreateReg() argument
1870 Op->Reg.ShiftExtend.Amount = ShiftAmount; in CreateReg()
1881 unsigned ShiftAmount = 0, in CreateVectorReg() argument
1886 auto Op = CreateReg(RegNum, Kind, S, E, Ctx, EqualsReg, ExtTy, ShiftAmount, in CreateVectorReg()
1926 unsigned ShiftAmount, in CreateShiftedImm() argument
1931 Op->ShiftedImm.ShiftAmount = ShiftAmount; in CreateShiftedImm()
2700 int64_t ShiftAmount = Parser.getTok().getIntVal(); in tryParseImmWithOptionalShift() local
[all …]
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| /external/llvm/lib/Target/Mips/ |
| D | MipsTargetStreamer.h | 121 void emitDSLL(unsigned DstReg, unsigned SrcReg, int16_t ShiftAmount,
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| /external/llvm/lib/Target/MSP430/ |
| D | MSP430ISelLowering.cpp | 736 uint64_t ShiftAmount = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue(); in LowerShifts() local
743 if (Opc == ISD::SRL && ShiftAmount) { in LowerShifts()
747 ShiftAmount -= 1; in LowerShifts()
750 while (ShiftAmount--) in LowerShifts()
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | LegalizeVectorOps.cpp | 827 SDValue ShiftAmount = DAG.getConstant(EltWidth - SrcEltWidth, DL, VT); in ExpandSIGN_EXTEND_VECTOR_INREG() local
829 DAG.getNode(ISD::SHL, DL, VT, Op, ShiftAmount), in ExpandSIGN_EXTEND_VECTOR_INREG()
830 ShiftAmount); in ExpandSIGN_EXTEND_VECTOR_INREG()
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| /external/llvm/lib/Analysis/ |
| D | InstructionSimplify.cpp | 2357 unsigned ShiftAmount = CI2->getValue().countLeadingOnes() - 1; in SimplifyICmpInst() local
2358 Lower = CI2->getValue().shl(ShiftAmount); in SimplifyICmpInst()
2362 unsigned ShiftAmount = CI2->getValue().countLeadingZeros() - 1; in SimplifyICmpInst() local
2364 Upper = CI2->getValue().shl(ShiftAmount) + 1; in SimplifyICmpInst()
2373 unsigned ShiftAmount = Width - 1; in SimplifyICmpInst() local
2375 ShiftAmount = CI2->getValue().countTrailingZeros(); in SimplifyICmpInst()
2376 Lower = CI2->getValue().lshr(ShiftAmount); in SimplifyICmpInst()
2387 unsigned ShiftAmount = Width - 1; in SimplifyICmpInst() local
2389 ShiftAmount = CI2->getValue().countTrailingZeros(); in SimplifyICmpInst()
2393 Upper = CI2->getValue().ashr(ShiftAmount) + 1; in SimplifyICmpInst()
[all …]
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